Demo Data from EDBT 2026 / reviewers in the wild / expert
Yung-Che Albert Shih
dblp:95/3638
· DBLP profile ↗
1ranked-venue papers
0as first author
0since 2021 · last 1993
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Electronic design automation · 67% Integrated circuit design · 33% |
Topics — the 3 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Integrated circuit design
interconnect |
0.0 | 1 | 1993 | Capacitance of top leads metal - comparison between formula, simulation, and experiment · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1993 |
Electronic design automation
interconnect modeling |
0.0 | 1 | 1993 | Capacitance of top leads metal - comparison between formula, simulation, and experiment · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1993 |
Electronic design automation › interconnect modeling
parasitic capacitance modeling |
0.0 | 1 | 1993 | Capacitance of top leads metal - comparison between formula, simulation, and experiment · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1993 |
Methods — techniques the papers use, named apart from their topics
two-dimensional numerical simulation · 0.0analytical formula · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1993 | Capacitance of top leads metal - comparison between formula, simulation, and experimentabstractThe parasitic interconnection capacitance can significantly degrade the performance of an IC. In this paper, the parasitic capacitance of the top leads with a protective overcoat (PO) dielectric is modeled. For a nitride only PO, the nitride increases the line-to-line capacitance component by the average of the nitride and underlying oxide dielectric constants with a maximum error of 11% according to two-dimensional numerical simulations. If the oxide thickness of the PO is greater than 0.2 mu m, then the line-to-ground component of capacitance will be within 10% of the value of a lead surrounded by oxide. The line-to-line component of capacitance can have an error of over 30% and a modification is required to reduce the error. Two modifications for the nitride/oxide PO are given; both increase the line-to-line capacitance by the fraction of nitride between the leads. The results of the modifications and simulation are compared to experiment. The two-dimensional simulations and formulas have a good fit to the experimental data.> Peter J. Wright, Yung-Che Albert Shih |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 2 |