Transformer-Based models have turned out to be very successful in many artificial intelligence (AI) tasks, outperforming traditional convolutional neural networks (CNNs), especially in the field of Natural Language Processing (NLP). Their success relies upon a self-attention mechanism which, when compared to CNNs, has a global rather than a local receptive domain. This article proposes an energy-efficient edge-device Transformer inference processor termed Smart Transformer Processing Element (STPE). Firstly, STPE sets up a Multi-Mode Indexing and Sparsity Scheme (MISS) for token association, and further reduces the computational load through in-situ computation; secondly, STPE exploits the Local Properties of Attention Mechanism (LPAM) to further reduce redundant and repetitive calculations in Transformer operations by means of a search band calculation and error correction mechanism; thirdly, STPE has designed a Quantization and Compression Parallel Method (QCPM) to improve the computing speed and hardware utilization under weak related (WR) token. Employing 28nm CMOS synthesis tools, the area of the proposed STPE processor is 7.33 mm2. Its peak energy efficiency is 84.15TOPS/W, which is 14.7 times higher than that of the H100 graphics processing unit (GPU) and 3.06 times higher than that of the most advanced Transformer processor.

This work presents an efficient decoding pipeline for neuromorphic implantable brain-machine interfaces (Neu-iBMI), leveraging sparse neural event data from an event-based neural sensing scheme. We introduce a tunable event filter (EvFilter), which also functions as a spike detector (EvFilter-SPD), significantly reducing the number of events processed for decoding by 192× and 554×, respectively. The proposed pipeline achieves high decoding performance, up to R2= 0.73, with ANN- and SNN-based decoders, eliminating the need for signal recovery, spike detection, or sorting, commonly performed in conventional iBMI systems. The SNN-Decoder reduces computations and memory required by 5 − 23× compared to NN-, and LSTM-Decoders, while the ST-NN-Decoder delivers similar performance to an LSTM-Decoder requiring 2.5× fewer resources. This streamlined approach significantly reduces computational and memory demands, making it ideal for low-power, on-implant, or wearable iBMIs.

Recently, Graph Neural Networks (GNNs) have shown great potential in terms of accuracy for problems that are well-described by graph representations, such as problems of path planning. However, implementing GNNs on mobile platforms is challenging as it requires a significant amount of computation and large memory. This article proposes a High-Performance Edge GNN Inference Processor termed GPE (GNN Processing Element). Firstly, GPE sets up Multi-Dimensional Indexing and Dynamic Pruning Schemes (MIDPS) for GNN networks, and achieves cross layer interconnection of multiple neighboring nodes via NOC (Network on Chip); secondly, GPE utilizes Graph Structure Adjacency Table Information (GSATI) of a GNN to further reduce redundant and repetitive calculations by means of repeated matching and difference transfer mechanisms; thirdly, GPE has a graph-based Multi Parallelism Simplification and Operation Method (MPSOM) to improve computing speed and hardware utilization under small data volumes. Using 28nm CMOS synthesis tools, the area of the proposed GPE processor is 5.37 square millimeters. Its peak energy efficiency is 21.5TOPS/W, which is 3.76 times higher than that of the H100 GPU (Graphics Processing Unit), while the energy consumption of GNN is 80.9% lower than the previous SOTA (State of Art) work.

This work investigates how the presence of thermal noise influences the response of simple networks incorporating an ideal memristor. First we study how a single noiseless memristor modulates noise at its input and how it manifests at its output. Then we extend our analysis to a generic resistor-memristor and capacitor-memristor network. The results reported are based on strong assumptions regarding the type of noise and the instantaneous linearity of the memristor networks, and should be viewed only as trend indicators.

This paper evaluated psychophysically an ultra-low-power, analog biomimetic cochlear-implant (CI) processor filterbank architecture, which was recently proposed and demonstrated in hardware. The architecture/strategy emulates the lateral inhibition (LI) mechanism by employing an automatic gain control (AGC) scheme that is coupled across One-Zero-Gammatone-Filter (OZGF) channels. The OZGF filtering and the coupled channel AGC were tested respectively in two experiments, where normal-hearing listeners were required to listen to sentences and recognise key words therein. The sentences were mixed with a steady background noise at signal-to-noise ratios (SNRs) of -6, -3 and 0 dB, and processed through a noise-excited envelope vocoder serving as the acoustic simulator of cochlear implants. In the first experiment, the OZGF filtering was compared with cascaded bandpass biquad filtering employed in recent attempts towards fully-implantable CI processing, in terms of the resulting intelligibility. The results showed that the sharply tuned OZGF response did not degrade intelligibility despite the very limited number (16) of channels used. In the second experiment, the sentences were processed in two multi-channel compression systems, one with the channel AGC coupled, whilst another uncoupled. The results showed that the AGC-coupled system was significantly advantageous, and the improvement averaged across the SNRs is 31 percentage points. Furthermore, this compressive system results in no significant decrease in intelligibility when compared to the linear filtering systems investigated in the first experiment. Thus, the coupled channel AGC may be considered as a potential solution to the limited spectral contrast of current CI systems, which may partially account for their noise-susceptibility.

This paper explains why charge- and flux-controlled memristor dynamics comply with Bernoulli's nonlinear differential equation. These devices are termed Bernoulli memristors. Based on the fact that their identified nonlinear dynamics can always be treated in a linearized manner, a general mathematical framework suitable for the systematic study of individual or networks of Bernoulli memristors can be developed. The paper details the novel mathematical framework and showcases its usefulness: 1) by applying it to obtain a closed-form expression of the output as an explicit function of the input for an example memristor model whose dynamics are described by a power law; 2) by determining analytically the harmonic content of the output of a Bernoulli memristor driven by a sinewave; 3) by investigating systematically the dynamics of networks of Bernoulli memristors connected either in series or in parallel; and 4) by assessing qualitatively the impact of series parasitic ohmic resistance on the dynamics of an ideal memristor.

Auditory filter models have a history of over a hundred years, with explicit bio-mimetic inspiration at many stages along the way. From passive analogue electric delay line models, through digital filter models, active analogue VLSI models, and abstract filter shape models, these filters have both represented and driven the state of progress in auditory research. Today, we are able to represent a wide range of linear and nonlinear aspects of the psychophysics and physiology of hearing with a rather simple and elegant set of circuits or computations that have a clear connection to underlying hydrodynamics and with parameters calibrated to human performance data. A key part of the progress in getting to this stage has been the experimental clarification of the nature of cochlear nonlinearities, and the modelling work to map these experimental results into the domain of circuits and systems. No matter how these models are built into machine-hearing systems, their bio-mimetic roots will remain key to their performance. In this paper we review some of these models, explain their advantages and disadvantages and present possible ways of implementing them. As an example, a continuous-time analogue CMOS implementation of the One Zero Gammatone Filter (OZGF) is presented together with its automatic gain control that models its level-dependent nonlinear behaviour.

In this paper a novel, practical, low-power, Class-AB companding hyperbolic sine(Sinh) integrator based on the harmonic mean law is presented. MOS transistors operating in their weak inversion region are used for low power and low supply voltage operation. All translinear loops are implemented using single-type devices allowing for fabrication on standard, twin-well CMOS processes. Detailed simulation results from Cadence IC Design Framework and the commercially available AMS 0.35 mum process parameters are reported and discussed. The proposed circuit achieves more than 120 dB of input dynamic range, and a frequency tunability of over 4 decades with a power consumption of less than 1.5 muW. In addition, head-to-head comparison with our previously reported (ISCAS '07) geometric-meanSinhintegrator is performed in an attempt to shed more light on the potential of this very promising class of current-mode companding filters.

This paper presents a CMOS image sensor intended for a novel optoelectronic retinal prosthesis. Each pixel acts as an independent oscillator, whose frequency is controlled by the incident light intensity. A 9 x 9 pixel array was fabricated in AMS 0.35 mum CMOS Opto Process. Each pixel's area amounts to 25600 mum2with the array occupying 2.89 mm2. Measured results show that the sensor achieves an overall dynamic range of 143 dB (from 34 mHz to 502 KHz) when the controlling bias current value varies from 0.2 pA to 5 muA respectively. Similarly, when the incident light intensity varies from 0.35 muW/cm2to 3.5 mW/cm2, the pixel's oscillation frequency changes from 0.24 Hz to 2.2 KHz respectively. This performance suffices for the optical stimulation of photosensitized RGCs.

Using a modified version of the linear cellular neural network (CNN) filtering paradigm recently proposed by the authors, we designed a nonseparable spatiotemporal bandpass filter with tunable spatiotemporal passband volumes. The filter presented here qualitatively resembles spatiotemporal receptive field models for the primary visual cortex. Numerical simulation results confirm the bandpass characteristic of our filtering network.

This paper proposes a miniaturized optoelectronic system suitable for the optical stimulation of genetically engineered retinal ganglion cells (RGCs) and focuses upon the synthesis and performance characteristics of a key circuit component needed for the programmable stimulator chip of the system: a wide tuning range voltage-controlled oscillator (VCO). The paper elaborates the synthesis and performance of a novel OTA structure which is used for the realisation of the needed wide tuning range VCO. The VCO has been designed and fabricated in AMS 0.35μm CMOS technology. Simulation results reveal a tuning range of more than 6 decades (70mHz to 0.2MHz).

This paper outlines the design and simulated performance of a novel, current-mode, companding, Class-AB,Sinhlossy integrator. PriorSinhfilter designs utilize current conveyor-like blocks which incorporate bothN-andP-type devices in alternate cascode arrangement to process the split-ted phases of the input. However, if these blocks were to be designed in weak inversion CMOS, the bulks of all the devices involved should be connected to their respective sources for accurate exponential/logarithmic conformity, which dictates the use of a triple-well process. Triple-well processes, apart from the fact that are not always available, have increased parasitics compared to twin-well ones, making the design and optimization of these already complicated filters a rather difficult one. In this paper, we present a newSinhlossy integrator circuit that uses (eitherN-or)P-type devices rendering it to be practically realizable in any standard twin-well process. The circuit has been designed in 0.35μm AMS CMOS process with all simulation results obtained from Cadence Design Framework®. The resulting lossy integrator exhibits a simulated input dynamic range greater than 120dB with only one integrating capacitor, while dissipating 0.3μWs of power.

this paper describes the development of a novel physiological platform aiming at the on-line, in-situ, multi-parametric, multi-channel, physicochemical, spatiotemporal monitoring of stem cell cultures. The three main operational components are: a) miniaturized electro-chemical (bio)sensors; b) real-time data acquisition system tailored to the sensor interfacing requirements and c) the bioreactor within which the stem cells are growing. It is believed that the totality of the platform constitutes a novel technological modality for the bioprocess engineer and can contribute to the harnessing of the potential of stem cells by enabling and/or facilitating the identification and classification of their proliferation and differentiation paths. This paper places emphasis upon the electronic hardware and software parts of the proposed "Intelligent Stem Cell Culture Systems" (ISCCS). The hardware of the measurement system is organized into three types of modules each capable of 16-channel real-time data acquisition. The three types of modules correspond to potentiometric, amperometric and ohmic types of sensors. The platform can support an arbitrary combination of such modules up to the number of eight, thus enabling the realization of a flexible and versatile system capable of providing up to 128 data acquisition channels for the physiological monitoring of the stem cell culture process. In other words, the measurement equipment can be configured to interface with up to eight different types of sensors each sensor monitoring a physiological quantity of relevance (e.g. glucose, lactate, ammonia, oxygen, pH etc.

This paper presents the synthesis, analysis and basic operation of a new VLSI-compatible CMOS current-mode synaptic circuit which implements the basic kinetics of a general chemical synapse in log-domain

This paper describes a procedure for the exact realisation of LC ladder finite transmission zeros in the log-domain. The synthesis of a third-order elliptic response proceeds by means of the recently identified Log-Domain State-Space (LDSS) and incorporates Ngarnmil's et. al. "log-domain differentiator". The resulting topology is compared to the pioneering design of Ferry and Roberts (1996) and is shown to provide a considerable improvement in linearity.

This paper attempts to estimate in an approximate way the impact of the basic bipolar process parameters upon harmonic distortion for the log-domain lossy integrator case. A symbolic transistor-level calculation is elaborated, based on the Charge-Control-Model (CCM) for the Bipolar Junction Transistor (BJT). Results correlating the BJT finite beta and parasitic base and emitter resistance with the harmonic distortion level present at the output are provided.