Spiking neural networks (SNNs) offer great potential for low-power intelligent computing owing to their event-driven nature, yet their deployment is limited by high inference latency and inefficient hardware utilization caused by temporal dependencies. Existing accelerators struggle to balance timesteps, accuracy, and energy efficiency, while hardware-oriented timestep compression remains underexplored. To address these challenges, this work presents STISA, a unified algorithm-hardware co-design framework featuring: 1) a Temporal Splitter Compression (TSC) technique with a Temporal Split Structure (TSS) to reduce temporal redundancy while preserving network dynamics; 2)a hardware-efficient spatiotemporal parallelism scheme, which co-optimizes dataflow and architecture through a Temporal-Prioritized Output-Stationary (TPOS) mapping and a flexible Block-Mux Streaming (BMS) architecture; and 3) a joint TSC-TPOS-BMS co-optimization framework featuring a bandwidth-aware resource allocation strategy to achieve balanced accuracy, latency, and energy efficiency across diverse network architectures. On the algorithmic side, TSC reduces synaptic operations by 24.44%-51.71% while achieving competitive accuracies of 96.38%, 81.10%, 68.51%, and 82.40% on CIFAR-10, CIFAR-100, ImageNet, and DVS-CIFAR10, respectively. On the hardware side, FPGA prototypes deliver up to$7.99\times $speedup, 30.4% power reduction, and 30.1% LUT reduction. Compared with state-of-the-art SNN accelerators, STISA achieves 0.16 GOPS/W/PE, demonstrating its scalability and superior energy efficiency for real-time SNN inference under constrained hardware resources.

Spiking Neural Networks (SNNs) have garnered considerable attention as a potential alternative to Artificial Neural Networks (ANNs). Recent studies have highlighted SNNs’ potential on large-scale datasets. For SNN training, two main approaches exist: direct training and ANN-to-SNN (ANN2SNN) conversion. To fully leverage existing ANN models in guiding SNN learning, either direct ANN-to-SNN conversion or ANN-SNN distillation training can be employed. In this paper, we propose an ANN-SNN distillation framework from the ANN-to-SNN perspective, designed with a block-wise replacement strategy for ANN-guided learning. By generating intermediate hybrid models that progressively align SNN feature spaces to those of ANN through rate-based features, our framework naturally incorporates rate-based backpropagation as a training method. Our approach achieves results comparable to or better than state-of-the-art SNN distillation methods, showing both training and learning efficiency.

Spiking Neural Networks (SNNs) represent a promising avenue for energy-efficient neuromorphic computing. Despite their potential, SNNs typically underperform compared to Artificial Neural Networks (ANNs) due to their complex spatio-temporal dynamics. To improve learning in these networks, researchers have developed various approaches that account for their unique characteristics—among them, normalization techniques have proven especially important. Recently, online learning algorithms have been explored for SNN training as they update network weights using only temporally local information, avoiding the high memory demands associated with Backpropagation Through Time (BPTT). However, the computational mechanism of online learning, which relies on temporally local information to update weights, hinders the application of integrating effective normalization techniques tailored for SNNs. In this work, we propose a Time-based Statistics Estimation (TSE) method to address limitations in existing normalization strategies for SNNs. We begin by establishing a systematic link between overall statistics and time-step-specific ones, leveraging the decomposability of key statistical measures. This insight allows our proposed TSE method to reliably estimate overall statistics using only recent iterations. Furthermore, the proposed method is compatible with both BPTT and online learning, consistently yielding strong performance across learning paradigms. Experiments on CIFAR-10, CIFAR-100, ImageNet, and DVS-CIFAR10 datasets demonstrate the superior performance of our method on both static and neuromorphic datasets. In particular, our method achieves state-of-the-art performance in online learning for SNN training.

Spiking Neural Networks (SNNs) are emerging as a brain-inspired alternative to traditional Artificial Neural Networks (ANNs), prized for their potential energy efficiency on neuromorphic hardware. Despite this, SNNs often suffer from accuracy degradation compared to ANNs and face deployment challenges due to fixed inference timesteps, which require retraining for adjustments, limiting operational flexibility. To address these issues, our work considers the spatio-temporal property inherent in SNNs, and proposes a novel distillation framework for deep SNNs that optimizes performance across full-range timesteps without specific retraining, enhancing both efficacy and deployment adaptability. We provide both theoretical analysis and empirical validations to illustrate that training guarantees the convergence of all implicit models across full-range timesteps. Experimental results on CIFAR-10, CIFAR-100, CIFAR10-DVS, and ImageNet demonstrate state-of-the-art performance among distillation-based SNNs training methods. Our code is available at https://github.com/Intelli-Chip-Lab/snn_temporal_decoupling_distillation.

Spiking Neural Networks (SNNs) exhibit exceptional energy efficiency on neuromorphic hardware due to their sparse activation patterns. However, conventional training methods based on surrogate gradients and Backpropagation Through Time (BPTT) not only lag behind Artificial Neural Networks (ANNs) in performance, but also incur significant computational and memory overheads that grow linearly with the temporal dimension. To enable high-performance SNN training under limited computational resources, we propose an enhanced self-distillation framework, jointly optimized with rate-based backpropagation. Specifically, the firing rates of intermediate SNN layers are projected onto lightweight ANN branches, and high-quality knowledge generated by the model itself is used to optimize substructures through the ANN pathways. Unlike traditional self-distillation paradigms, we observe that low-quality self-generated knowledge may hinder convergence. To address this, we decouple the teacher signal into reliable and unreliable components, ensuring that only reliable knowledge is used to guide the optimization of the model. Extensive experiments on CIFAR-10, CIFAR-100, CIFAR10-DVS, and ImageNet demonstrate that our method reduces training complexity while achieving high-performance SNN training. Our code is available at https://github.com/Intelli-Chip-Lab/enhanced-self-distillation-framework-for-snn.

Recent insights have revealed that rate-coding is a primary form of information representation captured by surrogate-gradient-based Backpropagation Through Time (BPTT) in training deep Spiking Neural Networks (SNNs). Motivated by these findings, we propose rate-based backpropagation, a training strategy specifically designed to exploit rate-based representations to reduce the complexity of BPTT. Our method minimizes reliance on detailed temporal derivatives by focusing on averaged dynamics, streamlining the computational graph to reduce memory and computational demands of SNNs training. We substantiate the rationality of the gradient approximation between BPTT and the proposed method through both theoretical analysis and empirical observations. Comprehensive experiments on CIFAR-10, CIFAR-100, ImageNet, and CIFAR10-DVS validate that our method achieves comparable performance to BPTT counterparts, and surpasses state-of-the-art efficient training techniques. By leveraging the inherent benefits of rate-coding, this work sets the stage for more scalable and efficient SNNs training within resource-constrained environments.

This article presents a novel circuit modeling method for online training and testing process of the neuromorphic chip crossbar array based on the resistive random access memory (RRAM). A modified RRAM compact model is developed to realize the fast and accurate update of multiple conductance levels. Two training mechanisms with and without write-verify scheme are modeled and investigated for classifying MNIST handwritten digits and both achieve a good recognition accuracy of more than 96%. The parasitic model of the unit cell of interconnects is constructed by the domain decomposition method (DDM) and the partial equivalent element circuit (PEEC) method, which is suitable to build up a crossbar array of any size. The impact of parasitic effects of interconnects on the recognition accuracy with and without write-verify scheme is analyzed and compared. The weights trained with write-verify scheme show better robustness to parasitic noises but training with write-verify scheme spends a longer time processing the same amount of data.

This article presents the theoretical analysis of passive charge sharing-based segmented successive-approximation-register (SAR) analog-to-digital converter (ADC), where the precise reference source in a capacitive digital-to-analog converter (CDAC) is replaced by a capacitor that is$\beta $times larger than its bit capacitor and precharged to the reference level, known as a reference charge reservoir (RCR). A segmented SAR-ADC uses a coarse SAR-ADC to compute some most significant bits (MSBs). Four methods, namely aligned switching (AS) with bitwise RCRs, AS with a subsample-wise RCR, detect-and-skip aligned switching (DAS-AS) with bitwise RCRs, and DAS-AS with a subsample-wise RCR are introduced for setting fine MSBs. Closed-form analytic expressions of the reference error due to the finite reference capacitance are derived and validated by behavioral modeling and circuit simulation of an 11-bit 50 MS/s segmented SAR ADC in 65-nm CMOS technology. The error expressions can be used to select one of the four methods for setting the fine MSBs and to determine$\beta $for the required linearity or for implementing digital circuitry for precise error correction.

This paper presents the analysis of bitwise and samplewise switched passive charge sharing for successive approximation register (SAR) analog-to-digital conversion (ADC). Closed-form analytic expressions of ADC transfer functions are derived based on charge conservation and validated by behavioral and schematic simulations. This leads to two elegant results for SAR ADCs with bitwise switched reference charge reservoirs (BS-RCRs). First, a binary-weighted SAR ADC implemented with BS-RCRs is transformed into a subradix-2 ADC. Second, the reference error caused by finite reservoir capacitance appears in the form of bit weight error. This error can be corrected digitally or by selecting a sufficiently large bit reference capacitance to bit weight capacitance ratio$\beta $. However, the reference error with samplewise switched reference charge reservoir (SS-RCR) is input dependent. In addition, an equivalent-circuit model-based analysis method is introduced, which shows more circuit intuition why BS-RCRs have better linearity than SS-RCR. A case study of an 11-bit 100-MS/s SAR ADC in 65-nm CMOS is presented.

A 12-bit 8-wire 8-level (12B8W8L) permutation coding scheme is designed for high speed parallel I/O interfaces. The proposed 12B8W8L permutation coding scheme improves pin efficiency to 150%, compared to 50% pin efficiency of the non-return-to-zero (NRZ) signaling, while keeping the encoding and decoding logic simple. It reduces the baud rate to 1/3 of NRZ signaling compensating for reduced SNR. The proposed coding scheme eliminates simultaneous switching noise (SSN) and reference voltage noise. A prototype transceiver is designed, simulated and verified in a 65 nm CMOS process, achieving 6 Gb/s/pin data rate and 0.99 pJ/bit energy efficiency over 4-inch FR4 channels.

This paper describes a comparator capable of detecting mV-range input voltage signals reliably using sub-nW power consumption. The comparator uses a current-mirror-based positive feedback and hysteresis to generate the mV-range threshold. It has three new ideas: (1) to use the input signal to bias the current mirror, which only activates the current mirror when the input signal reaches a detectable threshold; (2) to achieve dynamically controllable detectable threshold by using control signals to adjust the mirror transistor sizes; and (3) to use negative feedback to compensate the process-voltage-temperature variation. Preliminary SPICE simulation results using state-of-the-art 9HP (BiCMOS) have shown that the proposed hysteresis-based comparator can achieve the following performance metrics: 1) Very low comparator threshold (in the range of mV); furthermore, these threshold voltages can be programmable at run-time from a few to tens of mV. 2) Steep equivalent subthreshold slope in the range of sub-mV/decade. 3) Ultra-low leakage power (in the sub-nW range for a 0.1mV input voltage) and switching energy (in the nW range). The proposed hysteresis-based comparator only requires one standard logic supply source (working over 1V to 0.5V). Furthermore, initial simulations have shown that this comparator threshold is reliable over the process and voltage (PV) variations, and linearly proportional to temperature (T) variation.

A novel technique for implementing noise-shaping in time-interleaved SAR ADCs is presented. The noise-shaping is implemented passively and is easily reconfigured from first to second order. In both cases it achieves better SNR improvement than a conventional loop filter for a range of low OSR, and without the need for a power-hungry integrator. The architecture provides an energy-efficient ADC solution for a wide range of sample rates and resolution. To the best of the authors' knowledge, it is the first example of a noise-shaped ADC with more than two interleaved channels.