Robotic software can exhibit low performances even while running on allegedly powerful multi-core processor platforms. To find why is essential to guarantee the success of a mission. This paper presents an approach to analyze the processing resource demand of a ROS (Robotic Operating System) based robotic application. The AADL (Architecture Analysis and Design Language) language is used to model the application software, the hardware, and the deployment of the software components onto the hardware. The analysis of processor loads, and the checking of MIPS demand against MIPS capacity, is done with the OSATE2 tool, thanks to a few properties of the language. To set up those properties, a rapid profiling of the hardware and of the software components of the application is done, based on common Linux performance counting tools. The final accuracy is good enough to allow for a fast verification of the deployment options, and to help thinking or rethinking the software vs hardware architectures.

In this paper, we aim to bridge the gap between the energy efficiency of software and hardware video decoders by combining both DVFS and parallelism. For this purpose, we, first, propose an adaptive DVFS algorithm for energy efficient mono-core decoding of H.264 videos. The proposed solution uses metadata (normalized by MPEG) providing information about the upcoming workload. These metadata are processed within an adaptive filter to build dynamically an accurate complexity model used to calculate the minimal processor frequencies for decoding video frames while guaranteeing real time constraints. Then, we generalize the proposed DVFS to slice-based multi-threaded parallel video decoders on multi-core platforms. Our performance evaluations showed that the proposed algorithm for mono-core decoding is able to converge to an accurate complexity model (4 percent) in less than 1 second. Moreover, it is simple to implement, induces very low overhead and achieves up to 46 percent energy saving as compared to the ondemand Linux DVFS governor. On the other hand, joint use of parallelism and DVFS allows 720p software video decoding with only 17 percent more energy consumption as compared to a hardware video decoder.

In the embedded systems domain, obtaining performance and power consumption estimations is extremely valuable in numerous cases. This is particularly true during the design stage, as designers of complex embedded systems face an increasingly large design space. Secondary storage is a well-known performance bottleneck and has also been reported as an important factor of power consumption. Flash memory is the main secondary storage media in an embedded system and exhibits specific constraints in its usage. One popular way to manage these constraints is to use dedicated Flash File Systems (FFS). In this article, we propose a methodology to estimate the performance and power consumption of applicative I/Os on an FFS-based storage system within embedded Linux. The methodology is divided into three sequential steps. In the exploration phase, the main factors of an FFS storage system impacting performance and power consumption are identified. In the modeling phase, this impact is formalized into models. Finally, in the last phase, the models are implemented in a simulator named OpenFlash. OpenFlash allows obtaining performance and power consumption estimations for an applicative workload processed by the Linux FFS storage stack on an embedded platform. The simulator is validated against real measurements and the estimation error stays below 10%.

The concept of System of Systems (SoS) has become a key to handle the complexity of large scale systems designed in domains such as aerospace or defense. Virtual prototyping, by providing modelling and execution, increases the success of the SoS. Large scale systems involve heterogeneous modelling and execution formalism. Typical approaches based on types fail in offering the needed dynamicity to answer the virtual prototyping requirements. In order to bridge the existing gap between system models and execution tools, we suggest an approach based on roles and parser combinatory. Roles provide a dynamic coupling between modelling and execution allowing independent evolution of modelling and execution. Parser combinatory ease the integration of new modelling formalisms. This approach has been validated on a seafloor observatory project and lead to the implementation of a framework in Smalltalk.

This paper presents Open-PEOPLE, a hardware and software platform which aims to widen access to accurate power consumption measurement to the scientific community. The idea behind this platform is to centralize and abstract the instrumentation effort and the investment cost then allow geographically remote users to make power measurement remotely without requiring any specific costly hardware and/or software.

Mobile devices such as smart-phones and tablets are becoming the most important channel for delivering end-user Internet traffic especially multimedia content. One of the most popular multimedia application is video streaming. The video decoding process of this application is compute-intensive and is responsible of the consumption of a considerable part of the energy budget. Those mobile devices contain heterogeneous processing elements among-which we find Digital Signal Processors (DSP) and General Purpose Processors (GPP). In this context, the performance and energy estimation of those complex platforms is a difficult and time consuming task especially when considering both hardware and applicative parameters. In this paper, we propose a methodology for developing a unified high level video decoding performance and energy consumption analytical model for embedded heterogeneous platforms. This methodology is based on experimental measurements conducted on an embedded low-power platform. The developed model describes the performance and the energy consumption of H.264/AVC video decoding on both GPP and DSP in terms of video bit-rate, clock frequency and a set of comprehensive hardware and video related coefficients. It achieves a balance between a too abstract high level model and a detailed lower level one while guaranteeing a very good prediction properties (R-squared = 97%) for the tested videos. As a use case, we show that our model allows to accurately determine the bit-rate values for which video decoding on GPP is more energy-efficient than on DSP for a given platform.

Mobile devices such as smart-phones and tablets are increasingly becoming the most important channel for delivering end-user Internet traffic especially multimedia content. One of the most popular use of these terminals is video streaming. In this type of application, video decoding is considered as the most compute and energy intensive part. Some specific processing units, such as dedicated Digital Signal Processors (DSPs), are added to those devices in order to optimize the performance and energy consumption. In this context, the objective of this paper is to give a comprehensive and comparative study of the performance and energy consumption of video decoding application on embedded heterogeneous platforms containing a GPP and a DSP. To achieve this goal, a performance and energy characterization methodology for H.264/AVC video decoding is proposed. This methodology considers a large set of video coding parameters and operating clock frequencies to reflect different execution scenarios ranging from low-quality video decoding on low-end mobile phones to high-quality video decoding on tablets. The obtained results revealed that the best performance-energy trade-off highly depends on the required video bit-rate and resolution. For instance, the GPP can be the best choice in many cases due to a significant overhead in DSP decoding which may represent 30% of the total decoding energy in some cases. Some explanations about the obtained performance and overheads are given. Finally, guidelines on which processing element to choose according to video properties are also proposed.

Currently, designing low-power complex embedded systems is a main challenge for corporations in a large number of electronic domains. There are multiple motivations which lead designers to consider low-power design such as increasing lifetime, improving battery longevity, limited battery capacity, and temperature constraints. Unfortunately, there is a lack of efficient methodology and accurate tool to obtain power/energy estimation of a complete system at different abstraction levels. This paper presents a global framework for power/energy estimation and optimization of heterogeneous multiprocessor system-on-chip (MPSoC). Within this framework, a power modeling methodology is defined, and an open platform is developed. Our methodology takes into account all the embedded system relevant aspects; the software, the hardware, and the operating system. The platform stands for Open Power and Energy Optimization PLatform and Estimator (Open-PEOPLE). It includes diverse estimation tools with respect to their abstraction levels in order to cover the overall design flow. Starting from functional estimation and down to real boards measurements, our platform helps designers to develop new power models, to explore new architectures, and to apply optimization techniques in order to reduce energy and power consumption of the system. The usefulness and the effectiveness of the proposed power estimation framework is demonstrated through a typical embedded system conceived around the Xilinx Virtex II Pro FPGA platform.

This paper presents an energy estimation approach for embedded low power operating systems (OS). The methodology consists in characterizing and estimating energy and power overheads of a set of embedded OS basic services : scheduling, context switch and inter-process communication. We analyze the impact of hardware and software parameters like processor frequency and scheduling policy on the energy consumption. Then, energy and power models are extracted and the OS energy overhead of H264 application is estimated using the STORM tool. For the measurement setup, the hardware platform used is OMAP35x EVM board running Linux omap as operating system.

Designing low power complex embedded systems is now a critical challenge for a large number of electronic corporations. Low power is generally critical due to its impact on lifetime, battery longevity, battery capacity, temperature constraints, etc. Unfortunately, when a designer needs some power estimations about its design, the methods and tools which can help him are not sufficient. Indeed, there is a lack of efficient methodology and accurate tool to obtain power/energy estimation of a complete system at different abstraction levels. This paper addresses this problem and proposes a global framework for power/energy estimation and optimization of heterogeneous MultiProcessor System on Chip (MPSoC). This framework supports both a power modeling methodology and a power platform estimations which can help the designer to choose the best solution for his design. The methodology supported takes into account all the embedded system's relevant aspects; the software, the hardware, and the operating system. It includes several estimation tools with respect to their abstraction levels in order to cover the overall design flow. Starting from functional estimation and down to real boards measurements, our platform helps designers to develop new power models, to explore new architectures, and to apply optimization techniques in order to reduce energy and power consumption of the system. The usefulness and the effectiveness of the proposed power estimation framework are demonstrated through a typical embedded system conceived around the Xilinx Virtex II Pro FPGA platform.

In this contribution, we propose an efficient power estimation methodology for complex RISC processor-based platforms. In this methodology, the Functional Level Power Analysis (FLPA) is used to set up generic power models for the different parts of the system. Then, a simulation framework based on virtual platform is developed to evaluate accurately the activities used in the related power models. The combination of the two parts above leads to a heterogeneous power estimation that gives a better trade-off between accuracy and speed. The usefulness and effectiveness of our proposed methodology is validated through ARM9 and ARM CortexA8 processor designed respectively around the OMAP5912 and OMAP3530 boards. This efficiency and the accuracy of our proposed methodology is evaluated by using a variety of basic programs to complete media benchmarks. Estimated power values are compared to real board measurements for the both ARM940T and ARM CortexA8 architectures. Our obtained power estimation results provide less than 3% of error for ARM940T processor, 3.5% for ARM CortexA8 processor-based system and 1x faster compared to the state-of-the-art power estimation tools.

Embedded systems have to support more and more demanding multimedia applications. Heterogeneous multi-core architectures are now commonplace in mobile electronic devices. The impact on the power and energy consumption is tremendous; it has to be evaluated as soon as possible in the design process. Multimedia development frameworks are used to abstract the complexity of the hardware to the designer. In this paper, we propose a methodology to develop high-level performance and consumption models for multimedia streaming applications based on the GStreamer framework. Our approach is based on measurements of the power consumptions and execution times during the processing of combined video and audio streams. Performance and consumption models are build for various plugins instantiated in the corresponding GStreamer pipelines. The combination of estimations for all those plugins leads to a precise evaluation of the complete plugin performances. The precision of the models is evaluated against measurements for different real-life streaming applications.

This paper proposes an efficient Hybrid System Level (HSL) power estimation methodology for FPGA-based MPSoC. Within this methodology, the Functional Level Power Analysis (FLPA) is extended to set up generic power models for the different parts of the system. Then, a simulation framework is developed at the transactional level to evaluate accurately the activities used in the related power models. The combination of the above two parts lead to a hybrid power estimation that gives a better trade-off between accuracy and speed. The proposed methodology has several benefits: it considers the power consumption of the embedded system in its entirety and leads to accurate estimates without a costly and complex material. The proposed methodology is also scalable for exploring complex embedded architectures. The usefulness and effectiveness of our HSL methodology is validated through a typical mono-processor and multiprocessor embedded system designed around the Xilinx Virtex II Pro FPGA board. Our experiments performed on an explicit embedded platform show that the obtained power estimation results are less than 1.2% of error when compared to the real board measurements and faster compared to other power estimation tools.

This paper presents an innovative way to build flexible benchmarks based on micro-architecture independent characteristics. The proposed approach enables the testing and stressing of processors in order to reflect the real nature of applications and give meaningful information to the designers. The use of a limited number of basic blocks hand-coded in assembly, wisely chosen and arranged, enables to copy the behaviour of proprietary applications. An integer linear programming approach is used to find the number of basic blocks and their iterations. An enumerative method is used to build the basic blocks base. Our approach is used to generate synthetic test benches representative of the MediaBench applications suite. Real measurements conducted on an Intel processor show interesting and promising results, which will be discussed in details in this paper.

This paper presents a method that permits to quickly estimate the power consumption at the first steps of a systempsilas design. We present multi-level power models and show how to use them at different levels of the specification refinement in the component based AADL design flow. PET, a power estimation tool, is being developed in the frame of the European SPICES project. It first prototype gives, in the case of a processor binding, power consumption estimations, for software components in the AADL component assembly model, with a maximal error ranging roughly from 5% to 30% depending on the refinement level. We illustrate our approach with the power model of the PowerPC 405, and its use at different levels in the AADL flow.

The design of complex digital signal processing systems implies to minimize architectural cost and to maximize timing performances while taking into account communication and memory access constraints for the integration of dedicated hardware accelerators. Unfortunately, the traditional Matlab/Simulink design flows gather not very flexible hardware blocks. In this paper, we present a methodology and a tool that permit the high-level synthesis of DSP applications, under both I/O timing and memory constraints. Based on formal models and a generic architecture, this tool helps the designer in finding a reasonable trade-off between the circuit's latency and its architectural complexity. The efficiency of our approach is demonstrated on the case study of an FFT algorithm.

A high-level consumption estimation methodology and its associated tool, SoftExplorer, are presented. The estimation methodology uses a functional modeling of the processor combined with a parametric model to allow the designer to estimate the power consumption when the embedded software is executed on the target. SoftExplorer uses as input the assembly code generated by the compiler; its efficiency is compared to SimplePower's approach. Results for different processors (TI C62, C67, C55, and ARM7) and for several DSP applications provide an average error less than 5%.

We introduce a new approach to take into account the memory architecture and the memory mapping in behavioral synthesis. We formalize the memory mapping as a set of constraints for the synthesis, and defined a memory constraint graph and an accessibility criterion to be used in the scheduling step. We present a new strategy for implementing signals (ageing vectors). We formalize the maturing process and explain how it may generate memory conflicts over several iterations of the algorithm. The final compatibility graph indicates the set of valid mappings for every signal. Several experiments are performed with our HLS tool GAUT. Our scheduling algorithm exhibits a relatively low complexity that permits to tackle complex designs in a reasonable time.

In the digital and signal processing (DSP) applications, the main issue in system performance is strongly related to the memory subsystem characteristics and data positions. In such applications, exhaustive data analysis is often highly complex and time consuming whereas the actual bottlenecks are essentially due to the few largest data objects (arrays). Therefore, to ensure a good trade-off between analysis time and efficiency, we focus the optimization on these objects also called 'structures'. Our approach relies on a new graph formalism called 'data control flow graph' which analyzes an algorithm (written in C), and brings out data structure dependencies while retaining execution order constraints. Manipulating this graph allows to determine an optimized memory mapping according to a fixed memory hierarchy and thus to reduce bus activity, resulting in improved both execution time and energy consumption. This method is also planned to be extended to memory optimization by sizing both the memory hierarchy and the architecture.

We introduce a new approach to take into account the memory architecture and the memory mapping in the Behavioral Synthesis of Real-Time VLSI circuits. We formalize the memory mapping as a set of constraints for the thesis, and defined a Memory Constraint Graph and an accessibility criterion to be used in the scheduling step. We use a memory mapping file to include those memory straints in our HLS tool GAUT. Our scheduling algorithm exhibits a relatively low complexity that permits to tackle complex designs in a reasonable time. Several experiments are performed to demonstrate the efficiency of our method, and to compare GAUT with an industrial behavioral synthesis tool. We finally show how to explore, with the help of GAUT, a wide range of solutions, and to reach a good tradeoffs between time, power-consumption, and area.

This paper describes the building of a self-timed cell-set for an asynchronous router. The efficiency of such a routing scheme has been fully demonstrated. The description of the circuit's behavior in the form of communicating hardware processes leads to a modular representation of its architecture. Then specific cells are needed to actually implement those modules, both for control and data-path. This involves a full-custom design described in the present paper. Hazard-freeness relies on an original methodology respective to an accurate choice of delay models. Measured performances of the circuit and cells conclude the paper. Low power consumption is exhibited.

This paper describes the implementation of the self timed asynchronous router in a parallel machine. The heterogenous architecture of the machine is outlined, then the need for asynchronous operations is explained, and the interest in an asynchronous network control. The specification and VLSI design of the router are exhibited with its measured performances.