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Hirokazu Okano

dblp:95/4075 · DBLP profile ↗
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1ranked-venue papers
1as first author
0since 2021 · last 1987
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Theoretical computer science
1 paper
Coding theory · 100%
Computer architecture, parallel and distributed computing, and storage systems
1 paper
Integrated circuit design · 100%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Integrated circuit design
digital circuit design
0.011987
A Construction Method of High-Speed Decoders Using ROMS's for Bose-Chaudhuri-Hocquenghem and Reed-Solomon Codes · IEEE Trans. Computers 1987
Coding theory › error-correcting codes › cyclic codes
BCH and Reed-Solomon codes
0.011987
A Construction Method of High-Speed Decoders Using ROMS's for Bose-Chaudhuri-Hocquenghem and Reed-Solomon Codes · IEEE Trans. Computers 1987
Coding theory
error-correcting codes
0.011987
A Construction Method of High-Speed Decoders Using ROMS's for Bose-Chaudhuri-Hocquenghem and Reed-Solomon Codes · IEEE Trans. Computers 1987

Methods — techniques the papers use, named apart from their topics

galois field arithmetic · 0.0
YearPublicationVenuePosition
1987 A Construction Method of High-Speed Decoders Using ROMS's for Bose-Chaudhuri-Hocquenghem and Reed-Solomon Codes
abstract
In this paper, some efficient methods of solving equations over Galois field GF(2m) are proposed. Using these algorithms, decoders for triple-and quadruple-error-correcting Bose–Chaudhuri–Hocquenghem (BCH) codes are shown. More- over, we propose a new method of making high-speed decoders for double-error-correcting/triple-error-detecting BCH or Reed- Solomon (RS) codes by adding a simple error-identifying circuit to a decoder for double-error-correcting codes. By incorporating ROM's (read only memory) in a decoder, the complex logic circuits are eliminated and then we can easily construct a high- speed decoder. We evaluate the complexity of the decoders and show that each of them can be accommodated in a single chip LSI.
Hirokazu Okano, Hideki Imai
IEEE Trans. Computers1