In the field of very large-scale integration (VLSI) chip design, chip floorplanning plays a crucial role as it directly influences key optimization objectives such as placement wirelength. This, in turn, affects signal delay, power efficiency, routability, and overall cost. However, traditional reinforcement learning (RL) methods for chip floorplanning often oversimplify this complex and dynamic task. They tend to overlook the cascading effects of module placements and fail to fully comprehend the intricate interdependencies that are vital for making informed decisions. To address these challenges, we introduce an innovative approach that combines hypergraph graph convolutional networks (HyperGCNs) with deep recurrent Q-networks (DRQNs). This integration allows us to capture the nuanced dynamics and interconnected aspects of chip design more effectively. We enhance the traditional Markov decision process (MDP) model by incorporating a state characterization layer based on long short-term memory (LSTM) technology. Initially, HyperGCN efficiently encodes netlist information, simplifying complex graph structures into lower dimensional vectors, thereby enhancing knowledge processing. Subsequently, we treat the chip as an agent and apply the DRQN algorithm to optimize the module layout. DRQN’s LSTM utilizes a recurrent layer structure to grasp dependencies between modules, combined with the deep Q-network (DQN)’s optimization capabilities, enabling us to navigate the complexities of floorplanning. Our approach improves the state representation by encompassing a broader understanding of interconnected module characteristics. This allows our agents to make decisions that take into account the collective impact of module adjustments, rather than viewing each change in isolation. This comprehensive state representation, which includes diverse features and their evolving relationships, significantly enhances the decision-making capabilities of our agents. Our extensive experiments demonstrate that our method outperforms traditional heuristic-based and other learning-based floorplanning techniques. To the best of our knowledge, this is the first application of LSTM with DQN in circuit design, representing a significant advancement in the field.

High temperature or temperature nonuniformity has been considered as one of the most challenging problems in three-dimensional integrated circuits (3-D ICs). There have been many studies on the thermal issues in 3-D ICs floorplanning. However, most handcrafted heuristic algorithms require long iteration cycles, resulting in inefficient thermal management with no guarantee of good performance. Meanwhile, as modern integrated circuit design becomes increasingly complex, current floorplannings suffer from the “curse of dimensionality” and cannot optimize large-scale cases. Therefore, a novel thermal-aware fixed-outline 3-D IC floorplanning is proposed in this article. Since the temperature in a 3-D IC is mainly determined by a power distribution across tiers, this article proposes a deep${k}$-means clustering algorithm to cluster the modules and find a better cross-tier power distribution. This is an unsupervised machine-learning algorithm that can successfully cluster high-dimensional sample data. Then, in the global distribution (GD) stage, we not only consider the power consumption between the groups but also apply the number and area of through silicon vias (TSVs) to the clustering and analytical method in the multilevel framework. Inspired by the fact that finding the optimal TSV positions for multiple nets in the TSV assignment (TA) stage is essentially a way to maximize the benefits of nets in a competitive environment, game theory is applied to further reduce temperature and wirelength in this stage. We prove that it is an ordinal potential game, and then converge to the Nash equilibrium by the best response strategy. Experimental results demonstrate that the proposed method shows good performance in reducing the temperature of 3-D ICs, and its running time is quite fast.

High temperature and temperature nonuniformity pose significant challenges in 3-D integrated circuits (3-D ICs). Numerous studies have explored thermal issues in 3-D IC floorplanning. However, most existing handcrafted heuristic algorithms suffer from long iteration cycles, resulting in inefficient thermal management and no guarantee of optimal performance. In addition, with the increasing complexity of modern integrated circuit design, current floorplanning techniques encounter the “curse of dimensionality” and struggle to optimize large-scale cases. To address these challenges, this article proposes a novel end-to-end learning-based approach for thermal-aware fixed-outline 3-D IC floorplanning. In the tier assignment stage, we utilize a deep${k}$-means clustering algorithm to allocate modules to different tiers, aiming to achieve an improved cross-tier power distribution. In the global distribution (GD) stage, we formulate the floorplanning problem as a Markov decision process (MDP). By combining graph convolutional networks (GCNs) with a multiagent deep reinforcement learning (MADRL) algorithm, we optimize the positions of modules and through-silicon vias (TSVs), while incorporating an attention mechanism in the centralized critic to enhance cooperation among agents. Finally, in the TSV assignment (TA) stage, we refine the TSV positions using the MADRL algorithm, further reducing wirelength and temperature in 3-D ICs. Experimental results demonstrate that our proposed approach outperforms state-of-the-art heuristic-based 3-D IC floorplanner in terms of wirelength and temperature optimization.

Three-dimensional integrated circuit (3-D IC) technology has emerged as a solution to address the limitations of 2-D ICs. One critical component of 3-D ICs is the through-silicon via (TSV), which plays a crucial role in connecting signal nets and dissipating heat. The assignment of TSVs significantly impacts the wirelength and temperature of 3-D ICs. Although several studies have focused on the TSV assignment problem, most existing heuristic algorithms suffer from long iteration cycles and lack performance guarantees. Meanwhile, these methods struggle to optimize large-scale cases due to the curse of dimensionality inherent in complex IC designs. Recently, learning-based algorithms, particularly reinforcement learning (RL), have demonstrated success in solving various combinatorial optimization problems by leveraging past experiences. In this article, we propose attention-TSV assignment (ATT-TA), a novel TSV assignment method based on a multiagent deep RL (MADRL) algorithm. The TSV assignment problem is formulated as a Markov decision process (MDP), where each TSV layer serves as an independent agent. To enhance collaboration, we incorporate an attention mechanism that models and utilizes teammate strategies within a cooperative multiagent system. By applying multiagent systems, we mitigate the curse of dimensionality, while the attention mechanism enables adaptive modeling of joint strategies among agents. Notably, this is the first attempt to solve the TSV assignment problem using a MADRL algorithm. The experimental results demonstrate that compared with the state-of-the-art heuristic-based TSV assignment methods, the proposed ATT-TA approach consistently outperforms these methods in terms of wirelength and temperature optimization.