Logic synthesis is a crucial step in integrated circuit design, and area optimization is an indispensable part of this process. However, the area optimization problem for large-scale Fixed Polarity Reed-Muller (FPRM) circuits is an NP-hard problem. To address this problem, we divide Boolean circuits into small-scale circuits based on the idea of divide-and-conquer using the proposed grouping decomposition mechanism. Each small-scale Boolean circuit is transformed into an FPRM circuit by a polarity transformation algorithm. To ensure the circuit’s functionality remains unaffected, we integrate FPRM circuits into an FPRM and Boolean (RM-TB) dual logic circuit based on the proposed gate-level integration. However, the area optimization problem of RM-TB dual logic circuits is a multi-task, high-dimensional, and multi-extremal combinatorial optimization problem. Therefore, we propose a Multipopulation Multitasking Optimization Algorithm (MMuOA) that integrates self-evolution with a multitasking equilibrium optimizer and cross-task evolution through knowledge sharing and transfer. This forms a dynamic optimization framework for simultaneously searching for the optimal polarity corresponding to the minimal area of RM-TB dual logic circuits. Moreover, we propose an Area Optimization Approach (AOA) for an RM-TB dual logic circuit with the minimum area using the MMuOA. Experimental results based on the Microelectronics Center of North Carolina (MCNC) Benchmark test circuits demonstrate the effectiveness and superiority of the AOA compared to the state-of-the-art area optimization approach.

Logic synthesis is a crucial step in integrated circuit design, and power optimization is an indispensable part of this process. However, power optimization for large-scale Mixed Polarity Reed-Muller (MPRM) logic circuits is an NP-hard problem. In this article, we divide Boolean circuits into small-scale circuits based on the idea of divide and conquer using the proposed Dynamic Adaptive Grouping Strategy (DAGS) and the proposed circuit decomposition model (CDM). Each small-scale Boolean circuit is transformed into an MPRM logic circuit by a polarity transformation algorithm. Based on the gate-level integration, we integrate small-scale circuits into an MPRM and Boolean Dual Logic (RBDL) circuit. Furthermore, the power optimization problem of RBDL circuits is a multi-task, multi-extremal, high-dimensional combinatorial optimization problem, for which we propose an Adaptive Multi-task Intelligent Algorithm (AMIA), which includes global task optimization, population reproduction, valuable knowledge transfer (VKT), and local exploration to search for the lowest power for RBDL circuits. Moreover, based on the proposed Fast Power Decomposition Algorithm (FPDA), we proposed a Power Optimization Approach (POA) for an RBDL circuit with the lowest power using the AMIA. Experimental results based on Microelectronics Center of North Carolina (MCNC) Benchmark test circuits demonstrate the effectiveness and superiority of the POA compared to state-of-the-art POAes.