As transistor sizes continue shrinking, impacts of variability has become ever more paramount in circuit design and manufacturing. Their accurate representations in model cards help save design margins and provide appropriate guidelines in design technology co-optimization (DTCO). To address such a challenge, we propose a novel machine learning framework, Normalizing Flow-Based Joint Generative Model (NFGen), which generates a comprehensive model library from a limited number of model cards. Unlike traditional generative methods that focus on the marginal distribution of model card parameters, NFGen is the first model to approximate their joint distribution, which includes information on their correlation and thus enables closer representation of variability effects. In addition, we introduce two similarity metrics to rigorously evaluate the quality of generated model cards. Experimental results show that NFGen reduces overall error by 2x to 8x compared to state-of-the-art methods, validating its superiority in variability-aware DTCO.

Operational amplifier is one of the most important analog basic blocks. Existing automated synthesis strategies for operational amplifiers solely focus on the optimization of single topology, making them unsuitable for scenarios requiring batch synthesis, such as dataset augmentation. In this paper, we in-troduce TPC-GAN, a generative model for batch topology syn-thesis of operational amplifiers in accordance with performance specifications. To be specific, it incorporates a reward network of circuit performance into the adversarial generative networks (GANs). This enables direct synthesis of novel and feasible circuit topology meeting performance specifications. Experimental results demonstrate that our proposed method can achieve a validity rate of 98% in circuit generation, among which 99.7% are novel relative to the training dataset. With the introduction of a reward network, a significant portion (82.8%) of the generated circuits satisfy performance specifications, which is a substantial improvement than those without. Transistor-level experimental results further demonstrate the practicality and competitiveness of our generated circuits with nearly 3x improvement over manual designs.

Yield optimization is ubiquitous in circuit design but remains elusive for advanced nodes. This is largely due to the dilemma between one’s limited resources and the mounting cost of transistor-level simulation in yield estimation. To address this challenge, we propose a novel framework (CorDBA) to optimize yield using the statistical corners of process variations. By introducing a novel corner extraction method, our approach decouples the yield optimization process from its expensive yield estimation. With the help of max-minimum optimization, efficient computation is then conducted on the statistical quantiles of circuit performance metrics. In addition, CorDBA enables sequential yield optimization at multiple stages, in which information from lower yield may be utilized in latter optimization of higher yield. We examine its effectiveness via experiments including analog and digital circuit, as well as circuit with emerging device. We found that CorDBA provides 3.6x speedup (in terms of SPICE simulations) over the state-of-the-art method with 134.7x improvements in robustness (in terms of standard deviation).

Yield estimation and optimization is ubiquitous in modern circuit design but remains elusive for large-scale chips. This is largely due to the mounting cost of transistor-level simulation and one's often limited resources. In this study, we propose a novel framework to estimate and optimize yield using Bayesian Neural Network (BNN-YEO). By coupling machine learning method with Bayesian network, our approach can effectively integrate prior knowledge and is unaffected by the overfitting problem prevalent in most surrogate models. With the introduction of a smooth approximation of the indicator function, it incorporates gradient information to facilitate global yield optimization. We examine its effectiveness via numerical experiments on 6T SRAM and found that BNN-YEO provides 100x speedup (in terms of SPICE simulations) over standard Monte Carlo in yield estimation, and 20x faster than the state-of-the-art method for total yield estimation and optimization with improved accuracy.

Topology is one of the dominant factors governing analog circuit performance but its automatic design remains elusive. Most analog circuit topology designs are largely dependent on human expertise or a limited set of classic structures. To explore the potential of AI-driven design of analog circuit, we propose an automatic generation and optimization workflow, TSO-Flow, for the behavioral-level design of three-stage operational amplifiers. To be specific, TSO-Flow employs an invertible graph generative model to transform discrete circuit topology into a continuous latent representation. By random sampling in the latent space, one can generate an ensemble of latent vectors which can be translated back to novel circuit topology. In contrast to previous methods, such forward and reverse transformations are analytically invertible and thus enable exact likelihood estimation for training. Furthermore, one can optimize the topology in the latent space where a surrogate model is introduced for performance prediction. We evaluate the proposed framework with state-of-the-art methods via experiments on three-stage operational amplifiers. The results demonstrate that TSO-flow provides up to 116% improvements on FoM, 61% reduction in power, 50% less simulations and an overall 5x efficiency enhancement over the baseline methods1.