In nanometer regime, the temperature's influences on the leakage power and heat conductance become significant and thus, should be taken into account in the full-chip 3D thermal analysis. In order to analyze and assess the interactions among the temperature, power and heat conductance, for the first time, this work proposes an iterative thermal analysis method TPG. TPG uses initial values of nodal power density vector P and heat conductance matrix G to solve the nodal temperature vector T. Then it refreshes P and G with the obtained T and further solves T with the refreshed P and G. Although the CG and ICCG algorithm are widely used to solve T with P and G, both converge slowly and need hundreds of iterations. As G needs refreshed and changes per iteration, this work proposes a fast precondition-solving algorithm FPSCG which uses the Double-Nested Fast Fourier Transformation as CG's precondition. Based on the GPU parallel computing, this work further proposes an efficient algorithm FPSCG_GPU. A large amount of experiments show: (1) FPSCG only needs 4-6 iterations to solve T each time. (2) Without any precision lose, FPSCG_GPU can achieve 8X and 14X speed-up over CG and ICCG. (3) Compared with present methods which partially consider T's influence on G or P, our TPG method considers all T/P/G interactions and obtains higher simulation results about the maximum temperature and chip power consumption.

As mega-scale power/ground (P/G) grids came into being, the IR drop analysis is of the daunting computational complexity. By taking the topological advantage of the structure P/G grids, this work uses the row-based analysis method to transform the mesh-circuit analysis into many parallel triangle-diagonal row-circuit analyses of far smaller complexity. Then, the Graphics Process Unit (GPU) is employed to fast solve these row circuits in the parallel style. And this work further employs the LU decomposition of the triple-diagonal matrix to increase the efficiency of our method. Experimental results show that our method out-performs the traditional methods implemented on CPU. For mega-scale P/G grids of 1-4 million nodes, our GPU-implemented method is 9-12 times faster than its CPU counterpart and 2-3 times faster than its OpenMP counterpart.

As technology scaling into the nanometer regime, the performance is accompanied by the ever-increasing chip power consumption, in which leakage power consumption has become a major factor. Based on temperature-electric coupling effect, we study the temperature-cooling and energy-saving algorithm for high-end multi-processor system-on-chip (MPSoC). This work proposes a TALO (temperature-aware leakage optimization) algorithm to schedule tasks for MPSoCs. TALO assigns high priority to the coolest processor when there are multi-processor can be used, reducing the temperature-electric coupling leakage power. Comparing with TALK and traditional DVS algorithm, experiments show TALO is more efficient in power consumption. It can reduce the leakage power up to 70 percents for MPSoCs in contrast with DVS algorithm. At the same time, TALO can help decrease the highest temperature of each processor in MPSoC. It can make the temperature of each processor 34degC lower than DVS systems.

Based on multi-grid and equivalent circuit methods, an efficient algorithm for open-defect analysis, called as FODA, is proposed in this paper to solve nodal voltage distribution for a P/G network of open defects. The FODA algorithm consists of three successive steps. The first step uses the equivalent circuit method and the multi-grid method to compact the circuit. The second step uses the SOR algorithm for solving the remaindering circuit. The SOR algorithm becomes our favor owing to high efficiency and easy coding. The third step back solves the cancelled node based on the voltage-known nodes. Experiments show that FODA is of high accuracy, low complexity, wide application, and so on. Compared with the general ICCG algorithm, FODA is 36X faster with the penalty of ignored accuracy loss(<0.03% on average), and can solve two additional test cases that is unsolved to ICCG.

In this paper, we propose a novel method for analyzing fewer hot spots in a chip. The method, called SNSOR (Single-Node Successive Over Relaxation), is based on a novel localized relaxed iterative approach to perform statistical analysis on one hot spot at a time. Based on SNSOR, we propose an approximation method, called ET-SNSOR (Electro-Thermal SNSOR), to deal with the electro-thermal coupling (ETC) effects. ET-SNSOR first uses the iterative method to update correlations from ETC, and then computes standard temperature deviations for hot spots, according to ETC and updated correlations. Experiments show that ET-SNSOR is three orders of magnitude faster than the Monte-Carlo method with small errors (less than 4.76% on maximum). It only takes an average of 0.18 second to analyze one hot spot statistically for a large test case of 1.3M nodes with ETC effects.

With IC technology scaling into nanometer regime, VLSI chips not only become much more complex but also suffer from visible process variations. As a result, statistical methods are replacing deterministic methods for power/ground (P/G) grid analysis and efficient local analysis methods are badly needed to cut down the analysis complexity. A novel single-node successive over relaxation (SN-SOR) analytical method is proposed to efficiently solve correlated resistor vectors and then directly compute voltage variations for question nodes of large IR drop. Compared with traditional global SOR methods, SN-SOR method shows visible advantages including locality, efficiency, and low memory complexity. Experiments show our method is average 30 times faster than the global SOR method with only 0.38% accuracy loss.

In this work, we modify the Alpha-Power Law to accurately simulate BSIM3-70nm gate delay on transistor level. Combined with efficient power analysis methods, we develop one transistor-level simulator to efficient estimate performance and power for CMOS gates consisting of heterogeneous transistors. Furthermore, we propose a novel transistor-level optimization engine consisting of two-step algorithms. The former gate-space algorithm uses the clustering strategy to cut down algorithm complexity. The latter transistor-space algorithm employs fine granularity to pursue reducing more power consumption. Experiments show the following advantages: 1. Our transistor-level simulator takes average 1.0ms (on an ordinary PM1.4G-256M laptop computer) to analyze one gate and can accurately estimate circuit delay with only 2-7% worst-case error. 2. Our methodology is so general that it can analyze and optimize heterogeneous circuit in which each transistor may have its own different VT0, channel width and length. 3. In the transistor-level width+VT0+length-sized optimization, our engine takes feasible running time (856.4s for C7552) to cut down 22.58%(average) and 43.02%(maximum) leakage power caused by gate-level optimum solution nearly without penalty of active power.

In today's power/ground(P/G) network design, on-chip decoupling capacitors(decaps) are usually made of MOS transistors with source and drain connected together. The gate leakage current becomes worse as the gate oxide layer thickness continues to shrink below 20Å. As a result, decaps will become leaky due to the gate leakage from CMOS devices. In this paper, we take a first look at the leaky decaps in P/G network optimization. We propose a leakage current model for practical decaps and also present a new two-stage leakage-current-aware approach to efficiently optimize P/G networks in a more area efficient way.

Power consumption has become a primary constraint of integrated circuit design. Many models have been proposed to evaluate dynamic and leakage power in every design level. However, how to accurately predict TPower, the total power with dynamic and leakage power included, for large-scale designs within reasonable time remains unsolved. In this paper, a new topic of vector extraction for power estimation is brought forward based on the distribution analysis of power consumption of different types. After extracted, a large number of vectors are compacted into much fewer without significant influence on the specified power property, which makes the application of accurate and fast simulator possible. For the purpose of validation, we use the method on average TPower vector extraction and obtain good experimental results.

This paper deals with area minimization of power network for very large-scale integration designs. A new algorithm based on efficient nonlinear programming techniques is presented to solve this problem. During the optimization, a penalty method, conjugate gradient method, circuit sensitivity analysis, and merging adjoint networks are applied, which enables the algorithm to optimize large circuits. The experiment results prove that this algorithm is robust and can achieve the objective of minimizing the area of power network in a short runtime.

Dual threshold voltage design is the most effective technique for reducing leakage current of integrated circuits. In this paper, we put forward an average leakage current macromodeling for dual-threshold circuits and propose two methods to conquer it, table-lookup based simulation and statistical analysis. The simulation is an efficient general-purposed method for leakage current estimation. For stochastic input circuits, a new statistical method is presented, which is much faster than the former one and can be used for very large circuits, because the method is based on input Signal probability and only one pass of circuit is needed. To validate these two methods, accurate leakage currents are also calculated using popular simulator HSPICE for comparison. Experiments on ISCAS85 and ISCAS89 benchmarks demonstrate that the errors between them can be limited under 4% and thousand folds of time to results can be saved.

Three efficient test power optimization algorithms for CMOS circuits are studied in this paper. First, for delay-fault test pattern sets of ISCAS89 benchmarks, this algorithm can cut down 37.5% or more test power than the simulation-based annealing algorithm. Second, because approaches which use the Hamming distance between two input test patterns, to optimize the test power, cannot reduce as much power for ISCAS85 benchmarks as expected, a novel optimization approach that uses the power of an ideal circuit without delay, to optimize the test power is presented. Experimental results demonstrate that our approach can cut down 70.8% more test power than present approaches. Third, the influence of undetermined test bits on test power optimization is studied by changing the number of undetermined bits in test patterns. Experimental results demonstrate that with the increase of undetermined test bits, the un-optimized test power markedly decreases.

The authors theoretically describe the monotonic increasing relationship between average powers of a CMOS VLSI circuit with and without delay. The power of an ideal circuit without delay, which can be fast computed, has been used as the evaluation criterion for the power of a practical circuit with delay, which needs more computing time, in such fields as fast estimation for the average power and the maximum power, and fast optimization for the low test power. The authors propose a novel simulation approach that uses delay-free power to compact a long input vector pair sequence into a short sequence and then, uses the compacted one to fast simulate the average (or maximum) power for a CMOS circuit. In comparison with the traditional simulation approach that uses an un-compacted input sequence to simulate the average (or maximum) power, experiment results demonstrate that in the field of fast estimation for the average power, the present approach can be 6–10 times faster without significant loss in accuracy (less than 3.5% on average), and in the field of fast estimation for the maximum power, this approach can be 6–8 times faster without significant loss in accuracy (less than 5% on average). In the field of fast optimization for the test power, the authors propose a novel delay-free power optimization approach for the test power. Experiment results demonstrate that, in comparison with the approach of direct optimization and the approach of Hamming distance optimization, this approach is of the highest optimization efficiency because it needs shorter time (16.84%) to obtain a better optimization effect (reducing 35.11% test power).