In this paper, we propose a current-injected five-stacked ring oscillator with virtual power switches for generating an on-chip clock to test broadband memory operations. Clock signals across a wide frequency range are required to evaluate the functionality and frequency-specific characteristics of memory devices. Ring oscillator circuits are known for being some of the simplest and smallest circuits for generating clocks. However, as technology advances and processes shrink, generating low-frequency clocks using only ring oscillators in terms of area and power becomes increasingly difficult. To address this challenge, we introduce current-injected stacked ring oscillators and control broadband frequencies using virtual power and a power switch connected to the virtual ground. Furthermore, we present two types of tri-state inverter control techniques to manage the duty cycles of both high-frequency and low-frequency clocks, ensuring clean duty control while optimizing area efficiency. The proposed circuit is designed using a 28nm FDSOI process with a supply voltage of 1.8V. The entire prototype chip covers an area of 0.00238mm2.

This article presents a boost converter based on a maximum power point tracking (MPPT) circuit, and a multicurrent detector (MCD), an offset cancellation circuit to achieve high efficiency over a wide range of input power. The proposed boost converter employs an MPPT design for adaptive on-time operation, which adjusts the on-time width to achieve maximum efficiency depending on the input voltage. In addition, a phase frequency detector-based offset cancellation method is proposed to minimize power loss by accurately sensing the current detector, thereby transferring power. Therefore, the proposed method achieves a significant efficiency improvement of up to 10 % by implementing high-precision offset cancellation with an offset level of approximately$5~\mu $A, which is significantly lower than the conventional MCD offset of over 60 mA of maximum offset current level. The proposed boost converter fabricated in a 130 nm Bipolar-CMOS-DMOS (BCD) process occupies an active area of 0.806 mm2 and can self-start with a minimum input voltage of 450 mV ($40~\mu $W) and achieve maximum efficiency of 92.7 %.

We propose a heterogeneously reconfigurable energy harvester which contains multiple energy harvesting (EH) blocks, each comprised of multiple EH circuits in parallel to be optimized for different input power ranges. Practical EH circuits have their own favorable input power range due to turn-on sensitivity and saturation effects. To account for this, we present the necessary conditions for efficient configuration of an energy harvester, and then propose an algorithm for optimal reconfiguration of the energy harvester. Furthermore, adaptive time switching and mode switching problems are formulated in order to maximize the average achievable rate under the self-powering condition. Our proposed energy harvester and algorithm can be applied to low-power Internet-of-Things (IoT) devices with wireless EH capability for self-sustainability, which will be a key enabler for realizing a battery-free IoT network.

This paper presents a dual-mode adjustable-high-gain transimpedance amplifier (TIA). The TIA is designed with a high sensitivity to current bio-signals for a fine-dust detection system Integrated Circuit (IC) based on the operation of a photodiode module with high gain amplifications. Gain adjustment is implemented by coarse gain steps using selective-loads with four different gain values and fine gain steps by 42 dBΩ during 16 fine steps. To improve the settling time, a capacitive compensation is applied for the last stage. An off-state circuitry is proposed to avoid any off-current leakage. This TIA is designed in a 0.18 μm standard CMOS technology, output reached high gains from 149 dBΩ up to 216 dBΩ with 67 dBΩ gain variation range, input referred noise less than 600 fA/√ Hz in low frequencies and less then 27 fA/√ Hz at 20 KHz, a minimum detectable current signal of 4 pA, and has a power consumption of 2.71 mW.

In this article, we propose a dual-mode simultaneous wireless information and power transfer (SWIPT) system with a deep-learning-based adaptive mode switching (MS) algorithm to exploit both advantages of single-tone and multitone SWIPT. For self-powering of low-energy Internet-of-Things (IoT) devices, a duty-cycling operation is used with nonlinear energy harvesting. For this, we employ a new energy-assisted single-tone modulation which simplifies the receiver structure for information decoding. Considering the symbol-error rate performance, we formulate an adaptive MS problem to maximize the achievable rate under the energy-causality constraint by adjusting the MS threshold. To relieve the computational burden of the receiver, we introduce asymmetric processing for adaptive MS, for which the transmitter adapts the communication mode based on the feedback from the receiver. We invoke deep learning for adaptive MS at the transmitter that iteratively updates the MS threshold in a long-term scale via deep long short-term memory (LSTM) recurrent neural network (RNN) while deciding on the communication mode and modulation index in a short-term scale. We demonstrate the achievable rate improvement under an energy-neutral operation while providing interesting insights into designing the adaptive MS algorithm for the dual-mode SWIPT system.

The problem of parameter mismatch in time-interleaved-analog-to-digital converters (TI-ADCs) has become a significant concern to guarantee output linearity. Several solutions have been presented for offset, gain, time skew, and bandwidth mismatches, but they can rely on hardware expensive methods. This article proposes an all-digital calibration algorithm for the TI-ADC bandwidth mismatch, which is capable of detecting the optimal correction coefficients for the derivative-based digital filters. The analyzed convergence logic further relaxes the hardware requirements. Moreover, numerical simulations and experimental results validate the calibration efficiency. A commercial 12-bit 3.6-GS/s two-channel TI-ADC was used to verify the proposed calibration algorithm under real conditions.

This paper presents a low power FSK transceiver with ADPLL based on direct modulation and integrated SPDT switch for Bluetooth low energy application. To ensure that the proposed low power transceiver can operate at 1 Mbps data rate, FSK modulation is implemented using an ADPLL with direct modulation technique. The SPDT switch is integrated to share the antenna and matching network between the transmitter and receiver, thus minimizing the system cost by reducing external components. The transceiver is implemented using 1P6M 55-nm CMOS technology. The die area of the transceiver with DC-DC converter is 1.79 mm2. The power consumption of the Tx and Rx are 6 and 5 mW, respectively. The noise figure of Rx is up to 6.8 dB with respect to channel frequencies. The phase noise of the ADPLL is −84.7 and −118.9 dBc/Hz at 100 kHz and 1 MHz offset from 2.44 GHz, respectively.

In this study, we proposed a novel technique to enhance the performance of the dynamic comparator. The pre-amplifier outputs are directly connected to the latching nodes through switches that are controlled by output logics. Hence, the path of static current will be disconnected after making decision. Comparing to the previous dynamic comparators, the proposed structure shows significant performance improvement. The comparator has been simulated in standard 90nm technology. Simulation results show that the proposed comparator is suitable for low power, high speed applications.

In this paper, we propose a dual mode simultaneous wireless information and power transfer (SWIPT) system in which a sensor node monitors the received power and adaptively controls the communication mode. To this end, we design two types of single and multi-tone waveforms and propose a new transceiver architecture that realizes adaptive power management and information decoding (adaptive PM-&-ID) module. On top of this, we implement adaptive PM-&-ID policy algorithm which reflects non-linear energy harvesting (EH) model for both single and multi-tone waveforms. Our newly designed SWIPT can be applied to Internet-of-Things (IoT) network with RF EH capability for self-powering, leading to battery-free network. Numerical results show that significant performance gain can be achieved by the proposed dual mode SWIPT over the existing SWIPT design.

In this paper, the analog front end (AFE) for an inductive position sensor in an automotive electromagnetic resonance gear control applications is presented. To improve the position detection accuracy, a coil driver with an automatic two-step impedance calibration is proposed which, despite the load variation, provides the desired driving capability by controlling the main driver size. Also, a time shared analog-to-digital converter (ADC) is proposed to convert eight-phase signals while reducing the current consumption and area to 1/8 of the conventional structure. A relaxation oscillator with temperature compensation is proposed to generate a constant clock frequency in vehicle temperature conditions. This chip is fabricated using a 0.18-$\mu \text{m}$CMOS process and the die area is 2 mm$\times 1.5$mm. The power consumption of the AFE is 23.1 mW from the supply voltage of 3.3 V to drive one transmitter (Tx) coil and eight receiver (Rx) coils. The measured position detection accuracy is greater than 99.8 %. The measurement of the Tx shows a driving capability higher than 35 mA with respect to the load change.

A fully on-chip, low-power and small area CMOS Relaxation Oscillator (ROSC) with voltage integral feedback structure and a new Bandgap Reference voltage (BGR) for accurate oscillation frequency independent of the PVT and comparator's delay variations is presented. The designed circuit uses a new bandgap reference to generate the reference voltage required by relaxation oscillator which allow variations due to voltage and temperature to be compensated. Another merit of this oscillator is that the phase noise at low-offset frequency is suppressed by the voltage integral feedback circuit. The frequency of the relaxation oscillator is determined by the RC response time. Thus, the current and capacitance are controlled by temperature and process compensation circuits to compensate for the frequency variation. The ROSC is implemented in a 0.18µm CMOS technology and its active area is 0.14mm2. The target frequency is 25MHz and current consumption is 22µA, where VDDis 1.8V. The oscillation frequency variation for VDDranges from 1.4 to 1.9V is 0.2% and for temperature ranges from −40 to 125°C is 0.18%.

This paper presents a multi-channel capacitive touch sensing unit for SoC applications. This unit includes a simple common processing unit and switch array to detect the touch sensing input by capacitive-time(C-T) conversion method. This touch sensor ASIC is designed based on the Capacitive-Time(C-T) conversion method to have advantages of small current and chip area, and the minimum resolution of the unit is 41 fF per count with the built-in sensing oscillator, LDO regulator and I2C for no additional external components. This unit is implemented in 0.18 um CMOS process with dual supply voltage of 1.8 V and 3.3 V. The total power consumption of the unit is 60 uA and the area is 0.26 mm2.

Recently, the investigation of the cognitive radio (CR) system is actively progressed as one of the methods for using the frequency resources more efficiently. In CR systems, when the frequency band allocated to the incumbent user is not used, the unused frequency band is assigned to the secondary user. Thus, the FFT input signals corresponding to the actually used frequency band by the incumbent user are assigned as '0'. In this paper, based on the fact that there are many '0' input signals in CR systems, a low-power FFT design method for NC OFDM is proposed. An efficient zero flag generation technique for each stage is first presented. Then, to increase the utility of the zero flag signals, modified architectures for memory and arithmetic circuits are presented. To verify the performance of the proposed algorithm, 2048 point FFT with radix-24SDF structure is designed using Verilog HDL. The simulation results show that the power consumption of FFT is reduced considerably by the proposed algorithm.