Demo Data from EDBT 2026 / reviewers in the wild / expert
Simon Mall
dblp:95/4969
· DBLP profile ↗
1ranked-venue papers
0as first author
0since 2021 · last 2007
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Graphics, computer vision, multimedia, augmented reality and games · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer graphics and multimedia
1 paper |
Rendering · 100% | |
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
GPUs and heterogeneous computing · 100% |
Topics — the 3 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Rendering
point-based rendering |
0.1 | 1 | 2007 | A hardware architecture for surface splatting · ACM Trans. Graph. 2007 |
Rendering › point-based rendering
surface splatting |
0.1 | 1 | 2007 | A hardware architecture for surface splatting · ACM Trans. Graph. 2007 |
GPUs and heterogeneous computing
graphics hardware |
0.1 | 1 | 2007 | A hardware architecture for surface splatting · ACM Trans. Graph. 2007 |
Methods — techniques the papers use, named apart from their topics
FPGA prototyping · 0.1EWA splatting · 0.1ASIC design · 0.1
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2007 | A hardware architecture for surface splattingabstractWe present a novel architecture for hardware-accelerated rendering of point primitives. Our pipeline implements a refined version of EWA splatting, a high quality method for antialiased rendering of point sampled representations. A central feature of our design is the seamless integration of the architecture into conventional, OpenGL-like graphics pipelines so as to complement triangle-based rendering. The specific properties of the EWA algorithm required a variety of novel design concepts including a ternary depth test and using an on-chip pipelined heap data structure for making the memory accesses of splat primitives more coherent. In addition, we developed a computationally stable evaluation scheme for perspectively corrected splats. We implemented our architecture both on reconfigurable FPGA boards and as an ASIC prototype, and we integrated it into an OpenGL-like software implementation. Our evaluation comprises a detailed performance analysis using scenes of varying complexity. Tim Weyrich, Simon Heinzle, Timo Aila, Daniel Bernhard Fasnacht, Stephan Oetiker, Mario Botsch, Cyril Flaig, Simon Mall, Kaspar Rohrer, Norbert Felber, Hubert Kaeslin, Markus Gross 0001 |
ACM Trans. Graph. | 8 |