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Michael D. Noakes

dblp:95/5141 · DBLP profile ↗
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3ranked-venue papers
2as first author
0since 2021 · last 1993
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 1 first-authorComputer networks · 1 · 1 first-authorSoftware engineering, systems software and programming languages · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Parallel and multicore computing · 62% Interconnection networks and networks-on-chip · 19% Distributed systems · 19%
Computer networks
1 paper
Network optimization and economics · 100%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Network optimization and economics › network design
link assignment
0.011993
An adaptive link assignment algorithm for dynamically changing topologies · IEEE Trans. Commun. 1993
Parallel and multicore computing
multicomputer
0.011993
The J-Machine Multicomputer: An Architectural Evaluation · ISCA 1993
Distributed systems
fault tolerance
0.011993
An adaptive link assignment algorithm for dynamically changing topologies · IEEE Trans. Commun. 1993
Interconnection networks and networks-on-chip
network interface
0.011993
The J-Machine Multicomputer: An Architectural Evaluation · ISCA 1993

Methods — techniques the papers use, named apart from their topics

distributed optimization · 0.0graph-theoretic algorithms · 0.0graph-theoretic algorithm · 0.0architectural simulation · 0.0application benchmarking · 0.0
YearPublicationVenuePosition
1993 The J-Machine Multicomputer: An Architectural Evaluation
abstract
The MIT J-Machine multicomputer has been constructed to study the role of a set of primitive mechanisms in providing efficient support for parallel computing. Each J-Machine node consists of an integrated multicomputer component, the Message-Driven Processor (MDP), and 1 MByte of DRAM. The MDP provides mechanisms to support efficient communication, synchronization, and naming. A 512 node J-Machine is operational and is due to be expanded to 1024 nodes in March 1993. In this paper we discuss the design of the J-Machine and evaluate the effectiveness of the mechanisms incorporated into the MDP. We measure the performance of the communication and synchronization mechanisms directly and investigate the behavior of four complete applications.
Michael D. Noakes, Deborah A. Wallach, William J. Dally
ISCA1
1993 An adaptive link assignment algorithm for dynamically changing topologies
abstract
An adaptive link assignment algorithm for the distributed optimization of dynamically changing network topologies is presented. The algorithm is responsible for determining the network connectivity by controlling the selection of links to be established and disconnected. This algorithm is designed to recover from predictable link outages as well as massive unpredictable failures. To minimize computational time complexity as well as to improve transient response. Some known graph-theoretic algorithms are utilized.>
Michael D. Noakes, J. Bibb Cain, John W. Nieto, Edwin L. Althouse
IEEE Trans. Commun.1
1992 The Message Driven Processor: An Integrated Multicomputer Processing Element
abstract
A description is given of the Message-Driven Processor (MDP), an integrated multicomputer node. It incorporates a 36-bit integer processor, a memory management unit, a router for a 3D mesh network, a network interface, a 4K*36-bit word static RAM (SRAM), and an ECC dynamic RAM (DRAM) controller on a single 1.1 M-transistor VLSI chip. The MDP is not specialized for a single model of computation. Instead, it incorporates efficient primitive mechanisms for communication, synchronization, and naming. These mechanisms support most proposed parallel programming models. Each processing node of the MIT J-Machine consists of an MDP with 1 Mbit of DRAM.>
William J. Dally, Andrew A. Chien, Stuart Fiske, Gregory A. Fyler, Waldemar Horwat, John S. Keen, Richard A. Lethin, Michael D. Noakes, Peter R. Nuth, D. Scott Wills
ICCD8