High-speed micro-processors are key elements in communication system-on-chip (SOC) products. The design of these processors is challenging because of the extreme performance, low power and low cost that is required for a competitive state-of-the-art implementation. In this presentation, we will give an overview of the engineering techniques and design methodologies that are used to produce world-class embedded application processors with very fast design turn-around times. We will identify the main challenges that designers face when trying to achieve the highest possible performance within a given power envelope. The new issues posed by state-of-the-art embedded cores in nanometer process nodes will be discussed and opportunities for innovative electronic design automation (EDA) solutions will be highlighted.

In this paper we extend the O-tree approach to handle rectilinear blocks. First we explore the properties of L-shaped blocks, then decompose rectilinear blocks into a set of sub-L-shaped-blocks. The properties of L-shaped blocks can be applied to general recti?linear blocks. In order to explore the optimal search thoroughly, we generate four direction O-trees. A heuristic optimization algorithm based on the four direction O-trees produces very good experiment results.

A synthesis environment for analog integrated circuits is presented that is able to drastically increase design and layout productivity for analog blocks. The system covers the complete design flow from specification over topology selection and optimal circuit sizing down to automatic layout generation and performance characterization. It follows a hierarchical refinement strategy for more complex cells and is process independent. The sizing is based on an improved equation-based optimization approach, where the circuit behavior is characterized by declarative models that are then converted in a sequential design plan. Supporting tools have been developed to reduce the total effort to set up a new circuit topology in the system's database. The performance-driven layout generation tool guarantees layouts that satisfy all performance constraints. Redesign support is included in the design flow management to perform backtracking in case of design problems. The experimental results illustrate the productiveness and efficiency of the environment for the synthesis and process tuning of frequently used analog cells.

The ordered tree (O-tree) representation has recently gained much interest in layout design automation. Different from previous topological representations of non-slicing floorplans, the O-tree representation is simpler, needs linear computation effort to generate a corresponding layout, and exhibits a smaller upper-bound of possible configurations. This paper addresses the problem of handling symmetry constraints in the context of the O-tree representation. This problem arises in analog placements, where symmetry is often used to match layout-induced parasitics and to balance thermal couplings in differential circuits. The good performance of our placement tool dealing with several analog designs taken from industry proves the effectiveness of our technique.

The expansion of the market for portable wireless communication devices has given a tremendous push to the development of a new generation of low-power radio frequency integrated circuit (RFIC) products. In this fast-growing environment where time-to-market constraints force tight schedules, having a good design methodology, innovation computer-aided design (CAD) tools, and a well-integrated design system are key factors for success. In this paper, we describe a design system developed to provide the designer with everything necessary to accurately predict the behavior of RFIC devices, including layout and package parasitic effects. We show how important a well-defined and integrated system is to manufacturing a design that meets specifications at the minimum cost, in the minimum time. A close link between schematic, models, and layout is of paramount importance to ensure the accuracy need for low-power RF design. We give an overview of the advanced methods and tools currently available for simulation and noise analysis of RF devices. Finally, we show a design example that obtained first-silicon success.

This paper addresses the problem of device-level placement for analog layout, focusing mainly on symmetry-related aspects. Different from most of the existent analog placement approaches, employing basically simulated annealing optimization algorithms operating on flat (absolute) spatial representations, our model uses a more recent topological representation called sequence-pair, which has the advantage of not being restricted to slicing floorplan topologies. In this paper, we explain how specific features essential to analog placement, such as the ability to deal with complex symmetry constraints (for instance, an arbitrary number of symmetry groups of cells), can be easily handled by employing the sequence-pair representation. Several analog examples substantiate the effectiveness of our placement tool, which is already in use in an industrial environment.

This paper addresses the problem of device-level placement for analog layout.Different from most of the existent approaches employing basically simulated annealing optimization algorithms operating on flat Gellat-Jepsen spatial representations [2], we are using a more recent topological representation called sequence-pair [7], which has the advantage of not being restricted to slicing floorplan topologies.In this paper, we are explaining how specific features essential to analog placement, as the ability to deal with symmetry and device matching constraints, can be easily handled by employing the sequence-pair representation.Several analog examples substantiate the effectiveness of our placement tool, which is already in use in an industrial environment.

A new approach towards performance-driven placement of analog integrated circuits is presented. The performance speci cations directly drive the layout tools without intermediate parasitic constraints. A simulatedannealing algorithm is used to drive an initial solution to a placement that respects the circuit's performance speci cations. During each iteration, the layout-induced performance degradation is calculated from the geometrical properties of the intermediate solution. The placement tool handles symmetry constraints, circuit loading e ects and device mismatches. The feasibility of the approach is demonstrated withapractical circuit example. 1. Overview The main concern in automated analog layout synthesis