In this article, we derive a practical limit on the maximum achievable selectivity of three commonly used Passive Switched-Capacitor (PSC) Infinite-Impulse Response (IIR) low-pass filter (LPF) topologies driven from a resistive source. We show that filter topology selection and component dimensioning aimed to improve the selectivity of these filters will necessarily degrade the Noise Figure (NF), revealing a selectivity versus NF trade-off. We subsequently capture this in selectivity versus NF graphs. These graphs quantify the limitations on achievable selectivity and NF for each topology given the number of filter poles, and graphically provide guidance in navigating the trade-off between them. The three considered topologies mainly differ in how the sampling capacitor resets, inverts, or holds its voltage between clock periods. We capture the handling of the sampling capacitor as a new design parameter. We derive a singular model to encompass the entire design space consisting of the three topologies, filter order (number of history/integration capacitors), clock frequency, and component dimensions. The model comprises an adjoint network with a state-space description and is used to analyze the filter transfer function (to quantify selectivity), input- and output-referred noise, and NF.

Digital Multiple-Input Multiple-Output (MIMO) receivers, exposed to strong co-channel interference, require high dynamic range Analog-to-Digital Converters (ADCs) and a highly linear RF front-end. Hybrid analog-digital beamforming can mitigate this co-channel interference by spatial filtering before the ADC and improve interference robustness. This paper demonstrates and characterizes this mitigation effect in detail utilizing Error Vector Magnitude (EVM) as a criterion. A 4-element 22 nm FD-SOI CMOS prototype MIMO Receiver chip is characterized with a linear 4-element dipole antenna array with half-wavelength spacing in the 2.4 GHz ISM-band. EVM measurements demonstrate the effectiveness of spatial filtering for co-channel interference mitigation and dynamic range extension. The receiver is exposed to interference while using different QAM formats (16-QAM to 256-QAM). It is demonstrated how interference reduces the acceptable-EVM input power range, while hybrid beamforming extends this range. This is done by extensive conductive measurements for reliable results, while also demonstrating an Over-the-Air (OTA) result.

In-band full-duplex sets challenging requirements for wireless communication radios, in particular their capability to prevent receiver sensitivity degradation due to self-interference (transmit signals leaking into its own receiver). Previously published self-interference rejection designs require bulky components and/or antenna structures. This paper addresses this form-factor issue. First, compact radio transceiver feasibility bottlenecks are identified analytically, and tradeoff equations in function of link budget parameters are presented. These derivations indicate that the main bottlenecks can be resolved by increasing the isolation in analog/RF. Therefore, two design ideas are proposed, which provide attractive analog/RF-isolation and allow integration in compact radios. The first design proposal targets compact radio devices, such as small-cell base stations and tablet computers, and combines a dual-port polarized antenna with a self-tunable cancellation circuit. The second design proposal targets even more compact radio devices such as smartphones and sensor network nodes. This design builds on a tunable electrical balance isolator/duplexer in combination with a single-port miniature antenna. The electrical balance circuit can be implemented for scaled CMOS technology, facilitating low cost and dense integration.

Digital intensive architectures allow for flexibly programmable frequency synthesis. Timing jitter and/or phase noise is an important quality criterion for synthesizers. This paper reviews fundamental limitations for jitter in digital frequency architectures, aiming at finding a basis to compare alternative architectures and optimize jitter performance. It motivates why the product of jitter variance and power consumption is a useful figure of merit (FoM) for optimization, based on fundamental physical limitations. Applying this FoM to multi-phase clock generation leads to the conclusion that circuits with low delay are preferred, favoring a shift register architecture ("ring counter") over a Delay Locked Loop. For a PLL a Jitter-Power FoM is also defined and we show that significant improvements have been made during recent years.

This work proposes a direct conversion transmitter architecture intended for cognitive radio applications. The architecture is based on the poly-phase multipath technique, which has been shown to cancel out many of the harmonics, sidebands and nonlinearity contributions of a power up converter using a large number of signal paths. This work proposes a design only using 8 paths which is able to achievethand 9thharmonic. This is done with a combination of duty cycle control of the Local Oscillator (LO) waveform and tunable filtering with only a first order roll-off.

Spectrum sensing is one of the key characteristics of a cognitive radio. Energy detection provides maximum flexibility by not relying on any prior knowledge, but suffers from an SNR-wall due to noise uncertainty. Crosscorrelation of the outputs of two receiver paths is a technique to reduce the noise level of the total receiver, and hence improves the SNR. The reduction of the noise is limited by correlated noise originating from shared components near the antenna. In this paper we explore the use of a separate antenna for each receiver for crosscorrelation spectrum sensing. One immediate advantage is that due to the removal of the splitter, which was necessary to interface the single antenna to two receivers, the SNR improves, significantly reducing the required measurement time. A lot of the noise correlation can be removed, leading to a lower residual noise floor. The noise at each antenna will still be partially correlated due to mutual coupling, spatial noise correlation and man-made noise. We show that some signal power can be lost in the sensing process due to partial decorrelation of the signal at the two antennas. Fortunately, this seems to be a problem only in highly mobile environments, which makes the use of two-antenna crosscorrelation spectrum sensing an interesting solution towards more reliable energy detection.

This paper shows that the group delay of a delay circuit does not give sufficient information to predict the delay vs. frequency. A new criterion (fφ=0) is proposed that characterizes the delay variations over a specified frequency range. The mathematical derivation of fφ=0for a single delay block and a cascade of delay blocks is shown. As examples the criterion is applied to the design of an RC and LC delay block. Delay predictions based on fφ=0compared with simulation results, showing reasonable agreement.

Networks on chips (NoCs) are becoming popular as they provide a solution for the interconnection problems on large integrated circuits (ICs). But even in a NoC, link-power can become unacceptably high and data rates are limited when conventional data transceivers are used. In this paper, we present a low-power, high-speed source-synchronous link transceiver which enables a factor 3.3 reduction in link power together with an 80% increase in data-rate. A low-swing capacitive pre-emphasis transmitter in combination with a double-tail sense-amplifier enable speeds in excess of 9 Gb/s over a 2 mm twisted differential interconnect, while consuming only 130 fJ/transition without the need for an additional supply. Multiple transceivers can be connected back-to-back to create a source-synchronous transceiver-chain with a wave-pipelined clock, operating with 6sigma offset reliability at 5 Gb/s.

This paper shows that, for a given power budget, a shift register based multi-phase clock generator (MPCG) generates less jitter than a delay-locked loop (DLL) equivalent when both are realized with current mode logic (CML) circuits and white noise is assumed. This is due to the factor that the shift register MPCG has no jitter accumulation from one clock phase to the other as in the DLL based MPCG. For N-phase clock generation, the shift register MPCG needs a reference clock with N times higher frequency and thus requires a VCO with higher frequency than the DLL counterpart. However, we can show that this does not lead to additional power consumption.

Nonlinearity and time-variance in radio frequency (RF) circuits leads to unwanted harmonics and intermodulation products, e.g. in power amplifiers and mixers. This paper reviews a recently proposed multipath polyphase circuit technique which can cancel such harmonics and intermodulation products. This will be illustrated using a power upconverter IC as an example. The upconverter works from DC to 2.4 GHz, and the multipath polyphase technique cleans its spectrum up to the 17th harmonic, keeping unwanted spurious responses more than 40dB below the carrier. The technique can also be useful for other applications, and some possible applications will be discussed.

CMOS radio receiver architectures, based on radio frequency (RF) sampling followed by discrete-time (D-T) signal processing via switched-capacitor circuits, have recently been proposed for dedicated radio standards. This paper explores the suitability of such D-T receivers for highly flexible software-defined radio (SDR) receivers. Via symbolic analysis and simulations the authors analyze the properties of D-T receivers, and show that at least three challenges exist to make a D-T receiver work for SDR: 1) the sampling clock frequency is related to the radio frequency, complicating baseband filter design; 2) a frequency-dependent phase shift is introduced by pseudo-quadrature and pseudo-differential sampling; 3) the conversion gain of a charge sampling front-end is strongly frequency-dependent. Compared to a mixer based radio receiver, extra costs are needed to solve these problems.

Crosstalk limits the achievable data rate of global on-chip interconnects on large CMOS ICs. This is especially the case, if low-swing signaling is used to reduce power consumption. Differential interconnects provide a solution for most crosstalk and noise sources, but not for neighbor-to-neighbor crosstalk in a data bus. This neighbor-to-neighbor crosstalk can be reduced with twists in the differential interconnect pairs. To reduce via resistance and metal layer use, we use as few twists as possible by placing only one twist in every even interconnect pair and only two twists in every odd interconnect pair. Analysis shows that there are optimal positions for the twists, which depend on the termination impedances of the interconnects. Theory and measurements on a 10-mm-long bus in 0.13-$\mu$m CMOS show that only one twist at 50% of the even interconnect pairs, two twists at 30% and 70% of the odd interconnect pairs, and both a low-ohmic source and a low-ohmic load impedance are very effective in mitigating the crosstalk.

Opamp-RC integrators built with linear resistors and capacitors can achieve very high linearity. By means of a switched resistor, tuning of the RC time-constant is possible via the duty-cycle of the clock controlling the switched resistor. This paper analyzes the effect of opamp slew rate limitations on the distortion of a switched-resistor lossy opamp-RC integrator. We show via analysis and simulations that the use of two sets of switched resistors instead of one relaxes the opamp slew rate requirements, and reduces the resulting distortion significantly.