Analog to Digital Converters based on Voltage Controlled Oscillators are assumed very tolerant to sampling clock inaccuracies. This is due to the first-order shaping of sampling-induced errors, which appear indistinguishable from VCO phase quantization errors. A closer look to VCO-ADCs reveals that jitter errors can be problematic under different kinds of inputs and are affected by circuit impairments. This paper theoretically analyzes the behavior of pseudo differential VCO-ADCs in the presence of clock jitter and provides simulations of practical cases. In spite of being noise-shaped, the error induced by jitter is shown to depend on the input signal power. Afterwards, we analyze how VCO gain mismatch and offset among oscillators can affect clock jitter robustness. Also, in-band noise degradation due to out-of-band signal interferers is described.

A well established analysis technique of low-pass Sigma-Delta modulators is based on the white noise model, where quantization noise is assumed a uniformly distributed random signal. However, Sigma-Delta modulators exhibit numerous nonlinear effects that the white noise model fails to explain. Recently, a different way of describing low-pass Sigma-Delta modulators has been developed, establishing its similarities with VCO-based ADCs. A key idea in this new representation is the concept of the Pulse Frequency Modulation equivalent of a low-pass Sigma-Delta modulator. This paper reviews this new description with a simplified and intuitive approach and proposes new applications of the PFM analysis to other Sigma-Delta modulator architectures such as Band-Pass and Multistage modulators.

Voltage controlled oscillators (VCOs) were demonstrated to be an efficient hardware alternative to analog integrators in supply constrained nanometer CMOS technologies. Notably, various filter designs have found applications in voice feature extraction and communication systems. However, a deep understanding of the trade-offs in their design and their system-level limitations has not yet been described. This paper proposes an analysis of linear filters approximated using VCO-based integrators and provides insights in the design aspects of these systems.

One of the limitations of conventional VCO-ADCs is the restriction to first-order noise shaping. True VCO-ADC architectures have been proposed to increase the noise-shaping order by cascading several VCO integrators, but without requiring analog feedback loops. A high noise-shaping order allows to reduce the input VCO frequency compared to a conventional VCO-ADC with similar dynamic range, which improves power consumption. Prior-art True VCO-ADC architectures represent state variables either with a unity-weighted code or with a single-bit. Unity-weighted encoding is a natural choice when ring oscillators are selected as loop filter integrators. However, chip area restrictions force unity-weighted state variables to have few levels. A reduced number of levels in the state variables limits the dynamic range of True VCO-ADCs. In this paper, we experimentally demonstrate a second-order audio VCO-based ADC that uses ring oscillators as integrators but employs Gray and binary encoded state variables. As a consequence, the complexity and area of the True VCO-ADC architecture is reduced, breaking the barrier that limits the dynamic range of prior designs. The proof-of-concept chip shows a dynamic range of 103 dB achieving a peak SNDR of 76.5 dB-A with a power of 250$\mu$W occupying 0.095$\text{mm}^2$in 130 nm CMOS.

This paper introduces a unique asynchronous digital version of the widely recognized LIF neuron model, which is commonly used in spiking neural networks. This proposed circuit provides a technologically scalable alternative to conventional analog implementations. Despite utilizing digital logic, the neuron circuit employs internal variable representations that are rate-encoded as spike trains. This approach simplifies the internal circuitry by eliminating the need for arithmetic circuits and minimizes power consumption, achieving a figure of merit of 310 fJ/SOP. The programmability of the parameters, combined with these features, facilitates the use of off-chip gradient learning techniques without performance degradation due to PVT and mismatch variations during deployment.

This paper introduces a new CMOS implementation of a spiking Leaky Integrate-and-Fire (LIF) neuron. The circuit does not require any analog circuit block such as comparators or current sources thanks to the use of a ring-oscillator as an integrator and a phase delay detector as threshold logic. The circuit admits both excitatory and inhibitory input spiking signals whose pulse width does not affect the computation. Instead of powering the ring oscillators from a power supply, the input spikes charge a capacitor bank which powers the ring oscillator. The paper describes the operation of the neuron analytically for the input integration and the membrane voltage decay. Also, a circuit-level simulation in 65nm CMOS technology has been performed, achieving a power efficiency of < 40fJ/spike.

Recently VCO-based filters have been used to implement feature extraction in voice recognition systems. Typically implemented filter structures embed the VCOs in a feedback loop. In these implementations, harmonic distortion has been observed in the output signal. This harmonic distortion has been attributed to ring oscillator nonlinearity but its origin stems from a system level problem. In this manuscript we will analyze this problem by looking at the cross modulation of Pulse Frequency Modulation (PFM) side-bands and we will explain how this creates the previously misunderstood harmonic distortion. Moreover, we will propose efficient techniques to mitigate these harmonic components and show that they can easily be implemented in hardware.

A ring-oscillator based circuit is proposed for features extraction tasks within smart speech recognition and voice activity detectors applications. The architecture performs all the operations needed for conventional features extraction but making use of only time-encoded based circuits in the analog domain. This results in a compact and simple structure, easily scalable and suitable for the deepest CMOS nodes leading for ultra-low and small solutions. The proposal is described theoretically and functionally checked with behavioral simulations in MATLAB. Additionally, the filtering stage is designed in a 65-nm process and validated with transient simulations providing promising results referring estimated power and area.

This work introduces a new VCO-ADC architecture. The power supply nodes of the inverters in a ring oscillator are sorted in two sets, and connected to two different input signals. We show in this paper that the oscillator frequency of such configuration reacts to the product of the two inputs. Therefore, the ring oscillator can be used both as a mixer and to digitally acquire the lowpass converted component. A first system-level approach is made to optimize the distortion by a proper number of taps in the ring oscillator. To confirm the system level predictions, some circuit simulations have been made. As a result, it is observed that VCO non-linearity limits the SNDR in a similar way as in conventional low pass VCOADCs. In a 65nm CMOS process, 55 dB of SNDR is achieved in a 5-MHz bandwidth for a 1 MHz downconverted signal, using a sampling clock of 2.5 GHz and input signals centered in 70 MHz and 71 MHz.

Digital sensors contain reconfigurable Sigma-Delta modulators that support different working modes. Depending on the timing of reconfiguration, high amplitude transients may appear at the sensor output. This article analyzes the transient response of discrete time Sigma-Delta modulators to find the optimal reconfiguration moment. It is shown that the transient is optimal when the first state variable of the loop filter is zero at the reprogramming instant. The optimal time is predicted with a pulse frequency modulator model. Finally, a set of general equations are given to predict the transient sequence for any modulator order and topology.

This paper presents a novel approach to analyze clock jitter influence in the performance of continuous-time sigma-delta modulators. The analysis is based on projecting all the signals and operations over an artificial time-base relative to the sampling clock, on which the sampling period can be considered constant. In the proposed time-base, clock jitter can be modeled as the modulation of the input signal frequency and the integrators gain. Unlike standard techniques, we do not rely on the feedback pulse properties, which enables a broader application of our technique to band-pass or VCO-based sigma-delta modulators. In this paper, we present the basic theory of this technique and its application to some practical examples, showing a good matching between prediction and numerical simulation.

The main limitation of voltage-controlled oscillator based analog-to-digital converters (VCO-ADC) is the VCO non-linear voltage-to-frequency response, especially with ring-oscillators. This issue strongly restricts the final resolution we are able to get from the converter. In addition, flicker noise is a limitation for low-bandwidth applications. We propose a novel way of compensating both the VCO non-linearity and the phase noise effects. By means of a time varying switched-capacitor circuit, we build a purely analog compensation loop where jitter clock and DAC non-linearity do not suppose a limitation. The loop is closed with an opamp that provides gain to the compensation operation. The idea is proposed theoretically and tested by simulations, showing a good performance for audio or sensing applications.

The parallelism between a first-order sigma-delta modulator and a VCO-based ADC allows to calculate the DFT of the sigma delta sequence using Pulse Frequency Modulation theory. This paper exploits this parallelism to propose a more general model that links continuous time sigma delta modulators of an arbitrary order with Pulse Frequency Modulators. This novel point of view also predicts the spectral contents of a sigma delta encoded sequence beyond the white quantization noise model. The quantization noise can be split in two components, a deterministic one representing the carrier harmonic sidebands of a Pulse Frequency Encoded signal and a noise shaped pseudorandom signal representing the sampling operation. We seize these findings to propose a conjecture on the stability of a sigma delta modulator.

This work describes a systematic way to implement a band-pass noise-transfer-function (NTF) in an analog-to-digital converter implemented with a voltage-controlled-oscillator (VCO-ADC). The approach is based on the pulse frequency modulation (PFM) interpretation of a VCO-ADC, where the NTF is defined by a suitable pulse shaping filter inserted after the VCO. In this work, we explain how this pulse shaping filter can be defined to implement a quadrature band-pass NTF. In addition to describing the best theoretical way to achieve this, we also propose a hardware implementation using a digital delay line whose outputs are decoded with two lookup tables (LUTs). This enables tuning the NTF in software. Transient simulations were made to validate the implementation and robustness of the proposed approach and a case study of the power consumption was made for the case of a 65-nm CMOS process. Due to the mostly digital circuit implementation, the proposed structure is suitable for even newer ultra deep submicron CMOS processes.

This paper shows how to enhance the resolution of a VCO based ADC by transforming a ring oscillator into a continuous-time maximum length sequence generator. The code spreading provided by the maximum length sequence can be decoded after sampling by a look up table. Compared to an M tap ring oscillator, an equivalent maximum length sequence generator enhances the resolution of the resulting ADC by a factor 2M/M. We derive the basic system analysis for this new ADC architecture and show a simulation example.

A theoretical approach to the problem of replicating continuous-time systems with frequency modulated oscillators is proposed. It has been shown that continuous time filters and especially, the loop filter of a sigma-delta modulator, can be implemented with VCOs and digital circuitry. The analysis of these architectures is usually based on the integral relationship between frequency and phase in an oscillator. However, the spectrum of a modulated oscillator contains components at the harmonics of the oscillation frequency that cannot be easily described using the phase-frequency relationship. We propose a model in which a VCO is considered a signal encoder instead of an integrator. This model is applied then to the design of a band pass-sigma delta modulator.

Capacitive or resistive sensors can be included in the feedback network of an oscillator to implement a data acquisition system. A higher sampling rate, compared with standard oversampled converters, is required to maintain a sufficient SNR in this case. In this paper, we propose an architecture based on a LC-CMOS oscillator and a digital interface that can be completely integrated on chip and satisfies low clock specifications of standard microphone capacitive interfaces. The complete system outputs one-bit bitstream at 15.53MHz and achieves SNR of 55.38dB for -26dBfs input tone.

The analytical formulation of the output DFT of an oversampled converter based on a VCO has been recently disclosed for the single-bit case. However, most practical VCO-ADCs are constructed with a multibit configuration using a multiphase ring oscillator architecture. This paper shows that the spectral properties of a single-bit VCO-ADC are retained in the multibit case if an equivalent model is employed. This means that similar equations used to study the performance of single-bit ring oscillator can also be applied to the multibit case. Also, a multibit PFM-ADC has been proposed as an alternative to a conventional VCO-ADC, showing differences in the output spectrum respect to the VCO-ADCs based on ring oscillators. This paper describes these differences and how to apply the previous equations to study the PFM-ADC architecture.

Oversampled ADCs based on voltage-controlled oscillators have been analyzed using statistical models inherited from sigma-delta modulation. This letter shows that the discrete Fourier transform of a VCO-ADC output sequence can be calculated analytically for single tone inputs. The calculation is based on the transformation of the VCO output into a pulse frequency modulated signal that can be represented by a trigonometric series. Knowledge of the VCO-ADC output spectrum allows accurate evaluation of the SNDR dependence with the VCO oscillation frequency and gain constant. The SNDR predictions of the proposed model have been compared to behavioral simulations displaying only a deviation of 0.7 dB.

High-resolution noise shaping ADCs are increasingly used in measurement of biopotential signals. This paper presents a novel low power low voltage ADC based on a Dual-Slope (DS) integrating quantizer. To reduce power consumption, the active RC integrator used in integrating quantizers has been replaced by a passive RC low pass filter. Hence, no operational amplifiers are needed. This simplification implies two drawbacks. The passive integrator limits noise shaping due to imperfect integration. Moreover, approximation of linear ramps by an exponential capacitor charge introduces distortion. This paper reveals that the most limiting factor is distortion instead of imperfect integration. A simple method is proposed to compensate the distortion.

We present a multi-stage noise shaping modulator that uses a continuous time first stage and a Gated Ring Oscillator (GRO)as second stage. A Pulse Width Modulator (PWM) and a Time-to-Digital converter (TDC) is used as time-based quantizer in first stage. The binary output of the PWM is reused to control the GRO, avoiding the distortion that would be introduced by a conventional VCO. The digital outputs of both stages are filtered out to remove first stage quantization noise as in any conventional multi-stage Sigma-Delta Architecture. The architecture is suitable to extend the bandwidth or the resolution of a low oversampling time-based Continuous Time Sigma-Delta Modulators (CTIAM) with a small amount of analog circuitry and low power consumption. A simulation example using a 2-1 architecture, 50MHz bandwidth and 2GHZ clock is presented, showing 76dB SNDR at system level.

This paper presents a new approach to reduce the out of band energy in a class D amplifier driven by a DAC. The proposed architecture is based on a Time Encoded Filter (TEF). The TEF operates as a discrete time linear system on the pulse widths of a PWM signal rather than on the amplitudes of a sequence. It only requires RC circuits, comparators and digital logic. Hence, it can be integrated along with the D/A converter. The main advantage of this approach is that the number of power inductors and capacitors of the off chip low pass filter may be reduced.

The challenges of analog electronics in nanometer CMOS have motivated the search for new data converter architectures. This paper is a in introductory survey of new options to implement data converters seizing the high speed digital logic featured by the newest technologies. Classical comparator based ADC's may replaced by ring oscillators or pulse width modulators which are then sampled by Time to Digital Converters (TDC), bridging analog design with custom digital design. Continuous time sigma delta modulators can be enhanced replacing the quantizer by some kind of voltage to time encoder and a high speed sampling digital device. The paper will be supported by some chip examples.

This work presents a design procedure for Continuous Time (CT) Cascade Sigma Delta Modulators (SDMs) using the Sturdy approach for Discrete Time Modulators, where the usual Digital Cancellation Filters are removed. The error cancellation mechanism is affected by excess loop delay in the CT approach. Special design considerations are derived and a specific design methodology is proposed. A 10-MHz bandwidth and 80-dB peak SNR example is designed and simulated using a 2-1 topology.

This paper describes a continuous time bandpass sigma delta modulator able to convert signals above the sampling frequency. The proposed architecture mitigates two of the problems associated with continuous time subsampling modulators. First, alias attenuation in the DACs is compensated by a resonator in the feedback path. In addition, the requirement of resonators whose Q factor depends on the subsampling ratio is relaxed by use of a transmission line in the loop filter. A practical implementation is proposed and simulated. Subsampling a narrow band signal at 2.25 fs, the proposed modulator achieves 60 dB of SNR with OSR = 128 using resonators with Q = 80.

This work presents experimental results of a 6th order band-pass continuous-time sigma-delta modulator that uses transmission lines as resonators. It has been implemented in 0.35mum SiGe BiCMOS technology. The modulator tolerates two clock cycles of excess loop delay and has similar clock jitter sensitivity to that of an equivalent switched capacitor solution. The ADC operates at a sampling rate of fs=184 MHz, consumes 62mW and, assuming an OSR=256, is able to convert with a maximum SNR=55dB signals centered both at 46 MHz and 138 MHz, due to its subsampling capabilities

This paper proposes a technique to spectrally shape the clock jitter noise that is contributed by the feedback DACs in a continuous time sigma-delta modulator. A mathematical model and a simulation example are presented, showing a first-order shaping of the jitter noise

Clock jitter is an important source of error in highspeed current-steering D/A converters. A technique to compensate these errors is introduced. Simulations show a significant reduction to clock jitter sensitivity for the example of a sigma delta DAC with an analog bandwidth (ABW) of 30 MHz clocked at 360 MHz

This paper presents a class of continuous-time noise-shaping modulators whose noise transfer function (NTF) has a periodic number of zeroes, These modulators may be used to implement A/D converters for low-pass or band-pass signals. The modulators employ delay elements capacitors. The delay elements implementations are based on transmission lines.