Innovations in generative artificial intelligence (GenAI), particularly large language models (LLMs), are poised to revolutionize silicon design automation. This paper explores the transformative potential of LLMs in automating and enhancing various tasks within the silicon design process. It reviews the current applications of LLMs and their potential to automate silicon design tasks, proposing applications, providing a qualitative analysis of the readiness of the technology to support these applications and setting directions for future research.

Augmented Reality (AR) System-on-Chips (SoCs) have strict power budgets and form-factor limitations for wearable, all-day use AR glasses running high-performance applications. Limited compute and memory resources that can fit within the strict industrial design area footprint of an AR SoC, however, create performance bottlenecks for demanding workloads such as Pixel Codec Avatars (PiCA) group-calling which connects multiple users with their photorealistic representations. To alleviate this unique wearables challenge, 3D integration with hybrid-bonding technology offers energy-efficient 3D stacking of more silicon resources within the same SoC footprint. Implementing such 3D architectures, however, is another challenge as current EDA tools and flows offer limited 3D design control. In this work, we present a 3D design methodology for robust 3D clock network and datapath design using current EDA tools. To validate the proposed methodology, we implemented a 3D integrated prototype AR SoC housing a 3D-stacked Machine Learning (ML) accelerator utilizing TSMC SoIC™bonding technology. Silicon measurements demonstrate that the 3D ML accelerator enables running PiCA AR group call at 30 frames-per-second (fps) by 3D-expanding its memory resources by 4× to achieve 2× better energy-efficiency when compared to a 2D baseline accelerator at iso-footprint.

In the early design phase of a Deep Neural Network (DNN) acceleration system, fast energy and latency estimation are important to evaluate the optimality of different design candidates on algorithm, hardware, and algorithm-to-hardware mapping, given the gigantic design space. This work proposes a uniform intra-layer analytical latency model for DNN accelerators that can be used to evaluate diverse architectures and dataflows. It employs a 3-step approach to systematically estimate the latency breakdown of different system components, capture the operation state of each memory component, and identify stall-induced performance bottlenecks. To achieve high accuracy, different memory attributes, operands' memory sharing scenarios, as well as dataflow implications have been taken into account. Validation against an in-house taped-out accelerator across various DNN layers has shown an average latency model accuracy of 94.3%. To showcase the capability of the proposed model, we carry out 3 case studies to assess respectively the impact of mapping, workloads, and diverse hardware architectures on latency, driving design insights for algorithm-hardware-mapping co-optimization.

Test infrastructure of High-Density Three-Dimensional Integrated Circuits (HD 3D-IC) present a new test challenges because of the high interconnect density and the area cost for test features. In this work, we firstly present a pre-analysis of the testability of HD 3D-IC; we define the minimum acceptable 3D pitch value for a given technology to ensure the circuits testability. Afterwards, we propose an optimized DFT architecture allowing pre-bond and post-bond test for SRAM/Logic HD 3D-IC in line with the ongoing IEEE P1838 standard.

Modern computing applications require more and more data to be processed. Unfortunately, the trend in memory technologies does not scale as fast as the computing performances, leading to the so called memory wall. New architectures are currently explored to solve this issue, for both embedded and off-chip memories. Recent techniques that bringing computing as close as possible to the memory array such as, In-Memory Computing (IMC), Near-Memory Computing (NMC), Processing-In-Memory (PIM), allow to reduce the cost of data movement between computing cores and memories. For embedded computing, In-Memory Computing scheme presents advantageous computing and energy gains for certain class of applications. However, current solutions are not scaling to large size memories and high amount of data to compute. In this paper, we propose a new methodology to tile a SRAM/IMC based architecture and scale the memory requirements according to an application set. By using a high level LLVM-based simulation platform, we extract IMC memory requirements for a certain class of applications. Then, we detail the physical and performance costs of tiling SRAM instances. By exploring multi-tile SRAM Place&Route in 28nm FD-SOI, we explore the respective performance, energy and cost of memory interconnect. As a result, we obtain a detailed wire cost model in order to explore memory sizing trade-offs. To achieve a large capacity IMC memory, by splitting the memory in multiple sub-tiles, we can achieve lower energy (up to 78% gain) and faster (up to 49% gain) IMC tile compared to a single large IMC memory instance.

Neuromorphic computing is henceforth a major research field for both academic and industrial actors. As opposed to Von Neumann machines, brain-inspired processors aim at bringing closer the memory and the computational elements to efficiently evaluate machine learning algorithms. Recently, spiking neural networks, a generation of cognitive algorithms employing computational primitives mimicking neuron and synapse operational principles, have become an important part of deep learning. They are expected to improve the computational performance and efficiency of neural networks, but they are best suited for hardware able to support their temporal dynamics. In this survey, we present the state of the art of hardware implementations of spiking neural networks and the current trends in algorithm elaboration from model selection to training mechanisms. The scope of existing solutions is extensive; we thus present the general framework and study on a case-by-case basis the relevant particularities. We describe the strategies employed to leverage the characteristics of these event-driven algorithms at the hardware level and discuss their related advantages and challenges.

Energy-quality scalable systems are a promising solution to cope with the small energy budgets and high processing demands of mobile and Internet of Things applications. These systems leverage the error resilience of applications to obtain high energy efficiency, at the expense of tolerable reductions in the output quality. Hardware datapath operators able to reconfigure their precision and power consumption at runtime are key components of such systems. However, most implementations of these operators require manual, architecture-specific modifications and tend to have large power overheads compared to standard designs, when working at maximum precision. One promising design-independent alternative is dynamic voltage and accuracy scaling, whose adoption, however, is hindered by incompatibilities with standard design flows. In this paper, we propose a new methodology for the design of energy-quality scalable operators; our solution leverages runtime tuning of transistors threshold voltages to obtain a fine-grain control of the speed and power consumption of standard-cells within an operator. Thanks to the additional flexibility provided by this fine-grain knob, our method overcomes the main limitations of previous solutions, at the cost of a small area overhead. We demonstrate our approach on a 28 nm FDSOI technology; by exploiting the strong effect of back-gate biasing on threshold voltage, we achieve a power consumption reduction of more than 40% compared to the state-of-the-art, for the same precision.

Cu-Cu hybrid bonding offers very high density interconnects (pitch around 2 μm or less) in 3D stacking integrated circuits (HD 3D-IC), but the smaller the Cu pad size, the more the fabrication and bonding defects have an important impact on yield and performance. Defects such as bonding misalignment, micro-voids and contact defects at the copper surface, can affect the electrical characteristics and the life time of 3D-IC considerably. In this paper, we propose two complementary test and characterization structures dedicated to high density 3D-IC interconnects. The first test structure permits to measure the misalignment defect with a great accuracy and the second to measure the RC delay of a periodic signal applied to a daisy chain composed of 3D Cu-Cu interconnects. The measured misalignment values and propagation delays allows to detect Cu-Cu full open, misalignment, and micro-voids, in order to assess performance of high density 3D Integrated Circuit. Both test structures are implemented as BIST engines, which are integrated and controlled with IEEE 1687, for an overall negligible area cost.

In this paper some local stability results for an autonomous Long Short-Term Memory neural network model with respect to the origin are provided. In particular, it is shown through linearization that the local asymptotic stability conditions with respect to the origin only depend on one of the weight matrices. Simulations indicate that these local stability conditions greatly influence the behavior of the autonomous four-dimensional neural network in the region where each variable's values vary between minus one and one. Finally, some sufficient stability conditions for the nonlinear model are formulated as a convex program involving linear matrix inequalities.

Mobile and IoT applications must balance increasing processing demands with limited power and cost budgets. Approximate computing achieves this goal leveraging the error tolerance features common in many emerging applications to reduce power consumption. In particular, adequate (i.e., energy/quality-configurable) hardware operators are key components in an error tolerant system. Existing implementations of these operators require significant architectural modifications, hence they are often design-specific and tend to have large overheads compared to accurate units. In this paper, we propose a methodology to design adequate data-path operators in an automatic way, which uses threshold voltage scaling as a knob to dynamically control the power/accuracy tradeoff. The method overcomes the limitations of previous solutions based on supply voltage scaling, in that it introduces lower overheads and it allows fine-grain regulation of this tradeoff. We demonstrate our approach on a state-of-the-art 28nm FDSOI technology, exploiting the strong effect of back biasing on threshold voltage. Results show a power consumption reduction of as much as 39% compared to solutions based only on supply voltage scaling, at iso-accuracy.

Achieving the lowest possible operating voltage is needed to minimize the power consumption of a circuit but also to increase its reliability w.r.t hardware errors. An in-situ technique to estimate and reduce the design margins of a circuit is presented which significantly minimizes the operating voltage and tracks it during run-time operation of a circuit without failure. A DSP core embedding this technique has been fabricated and measured. Its Vminhas been estimated within +3.5%/-2.5% at nominal clock frequency (1600MHz), thus reducing by 19% its energy per operation.

In this paper, we present a high-density four-transistor (4T) static random access memory (SRAM) bitcell design for 3-D CoolCube technology platform based on 14-nm fully depleted-silicon on insulator MOS transistors to show the compatibility between the 4T SRAM and the 3-D design and the considerable density gain that they can achieve when combined. The 4T SRAM bitcell has been characterized to investigate the critical operations in terms of stability (retention and read) taking into account the post-layout parasitic elements. Thus, failure mechanisms are exposed and explained. Based on this paper, a data-dependent dynamic back-biasing scheme improving the bitcell stability is developed. A specific read-assist circuit is also proposed in order to enable a large number of bitcells per column in a memory array. Finally, the designed bitcell offers up to 30% area gain compared to a planar six-transistor SRAM bitcell in the same technology node.

Connected devices are getting attention because of the lack of security mechanisms in current Internet-of-Thing (IoT) products. The security can be enhanced by using standardized and proven-secure block ciphers as advanced encryption standard (AES) for data encryption and authentication. However, these security functions take a large amount of processing power and power/energy consumption. In this paper, we present our hardware optimization strategies for AES for high-speed ultralow-power ultralow-energy IoT applications with multiple levels of security. Our design supports multiple security levels through different key sizes, power and energy optimization for both datapath and key expansion. The estimated power results show that our implementation may achieve an energy per bit comparable with the lightweight standardized algorithm PRESENT of less than 1 pJ/b at 10 MHz at 0.6 V with throughput of 28 Mb/s in ST FDSOI 28-nm technology. In terms of security evaluation, our proposed datapath, 32-b key out of 128 b cannot be revealed by correlation power analysis attack using less than 20 000 traces.

In this paper we propose to give an overview of fine-grain design techniques we demontrated past years in our lab for power reduction in complex SoCs. Those works are based on Globally Asynchronous and Locally Synchronous systems in which each IP is an independent voltage and frequency domain. After having proposed some simple DFS architectures based on GALS architectures in 130nm technology, we extended our works to fine-grain Dynamic Voltage and Frequency Scaling architectures to reduce dynamic and static power reduction at 65 nm node. Furthermore, considering 32 nm deep submicron technologies, we demonstrated an Adaptive Voltage and Frequency architecture to compensate for in-die PVT variations. Area overhead and power reduction results are discussed all along the paper.

Nowadays, power consumption is one of the main limitations of electronic systems. In this context, novel and emerging devices provide new opportunities to extend the trend toward low-power design. In this survey article, we present a transversal survey on energy-efficient techniques ranging from devices to architectures. The actual trends of device research, with fully depleted planar devices, tri-gate geometries, and gate-all-around structures, allows us to reach an increasingly higher level of performance while reducing the associated power. In addition, beyond the simple device property enhancements, emerging devices also lead to innovations at the circuit and architectural levels. In particular, devices whose properties can be tuned through additional terminals enable a fine and dynamic control of device threshold. They also enable designers to realize logic gates and to implement power-related techniques in a compact way unreachable to standard technologies. These innovations reduce power consumption at the gate level and unlock new means of actuation in architectural solutions like adaptive voltage and frequency scaling.

The emerging SOI technologies provide an increased body bias range compared to traditional bulk technologies, opening new opportunities. From the power management perspective, a new degree of freedom is added to the supply voltage and clock frequency variation, increasing the complexity of the power optimization problem. In this paper, a method is proposed to manage the power consumed in an FD-SOI circuit through supply and body bias voltages, and clock frequency variation. Results for a Digital Signal Processor in STMicroelectronics 28nm FD-SOI technology show that the power reduction ratio can reach 17%.

Dynamic Power Management and Dynamic Voltage and Frequency Scaling have been investigated during the last decades to reduce the power consumption of electronic circuits and systems. This paper proposes a new implementation of dynamic frequency scaling to manage the power consumption based on the occupancy level of a FIFO in a communication link between two components. Based on control theory, the method is simple and application independent. The PI controller proposed here was first tested in the MAT LAB environment and then designed using VHDL. Simulations in the MATLAB environment and in ModelSim have allowed the validation of the control technique proposed. Being synthesized in technology FD-SOI 28nm using RC synthesis tool from Cadence, the control method presents only 10.8% of Silicon area overhead with 1.6% of power consumption reduction. This preliminary result is appealing because it has been obtained without voltage scaling that will improve the power gain even more.

Todays' MPSoC applications are requiring a convergence between very high speed and ultra low power. Ultra Wide Voltage Range (UWVR) capability appears as a solution for high energy efficiency with the objective to improve the speed at very low voltage and decrease the power at high speed. Using Fully Depleted Silicon-On-Insulator (FDSOI) devices significantly improves the trade-off between leakage, variability and speed even at low-voltage. A full design framework is presented for UWVR operation using FDSOI Ultra Thin Body and Box technology considering power management, multi-VT enablement, standard cells design and SRAM bitcells. Technology performances are demonstrated on a ARM A9 critical path showing a speed increase from 40% to 200% without added energy cost. In opposite, when performance is not required, FDSOI enables to reduce leakage power up to 10X using Reverse Body Biasing.

A fast and accurate statistical method that estimates at gate level the leakage power consumption of CMOS digital circuits is demonstrated. Means, variances and correlations of logic gate leakages are extracted at library characterization step, and used for subsequent circuit statistical computation. In this paper, the methodology is applied to an eleven thousand cells ST test IP. The circuit leakage analysis computation time is 400 times faster than a single fast-Spice corner analysis, while providing coherent results.

Ultra-Thin Body and BOX Fully-Depleted SOI (UTBB FD-SOI) technology is one of two candidate technologies for replacing Bulk technology at sub-20nm nodes. Although it represents a smooth transition from Bulk, i.e. being a planar technology with a similar gate stack and a simpler front-end-of-line process, it enables a reinforced process-design co-optimization thanks to Well engineering capability. This added degree of freedom has unleashed the creativity of designers and technologists, creating objects like ‘flip-Well’ and ‘single-Well’ logic gates. This paper presents the state-of-the-art of UTBB FD-SOI implementation strategies and solves the multi-VTconstrains thanks to innovative fine grain co-integration approaches.

Wireless sensor nodes that are self-powered by extracting their energy from their environment are a new opportunity for monitoring purpose. Since the available energy is not constant over time and due to very low harvested power levels, efficient energy and power management strategies are mandatory for improving their autonomy. At system level, scheduling algorithms are proposed to efficiently use multi power path architectures and avoid as much as possible the use of batteries. A data- and energy-driven architecture and its associated algorithm are presented achieving high efficiency due to fully adaptive scheme.

All mobile applications require high performances with very long battery life. The speed and power consumption trade-off clearly appears as a prominent challenge to optimize the overall energy efficiency. In Multiprocessor System-On-Chip architectures, the trade-off is usually achieved by dynamically adapting the supply voltage and the operating frequency of a processor cluster or of each processor at fine grain. This requires monitoring accurately, on-chip and at runtime, the supply voltage and temperature across the die. Within this context, this paper introduces a method to estimate, from on-chip measurements, using embedded statistical tests, the supply voltage and temperature of small die area using low-cost digital sensors featuring a set of ring oscillators solely. The results obtained, considering a 32nm process, demonstrate the efficiency of the proposed method. Indeed, voltage and temperature measurement errors are kept, in average, below 5mV and 7°C, respectively.

Asynchronous circuits are well known for their benefits in terms of dynamic power savings because asynchronous logic does not switch when inactive. Nevertheless, in deep-submicron technologies, leakage currents have become an increasing issue, and thus, asynchronous circuits need to focus on static-power-consumption reduction. In this paper, we propose an innovative way to detect incoming asynchronous activity. Associated to an automatic power regulation, it efficiently reduces the supply voltage and, thus, both energy per operation and leakage currents. The proposed technique has been applied to an asynchronous network-on-chip node and successfully implemented in an ST Microelectronics CMOS 65-nm technology.