Kengo Nishino

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Demo Data from EDBT 2026 / reviewers in the wild / expert

dblp:95/6924 · DBLP profile ↗

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1ranked-venue papers

0as first author

0since 2021 · last 2001

—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems

1 paper

Processor architecture and microarchitecture · 100%

Topics — the 3 heaviest of 3, each with the papers that count most for it

Topic	Papers	Last	Evidence papers
Processor architecture and microarchitecture › instruction scheduling dynamic instruction scheduling	1	2001	A high-speed dynamic instruction scheduling scheme for superscalar processors · MICRO 2001
Processor architecture and microarchitecture instruction scheduling	1	2001	A high-speed dynamic instruction scheduling scheme for superscalar processors · MICRO 2001
Processor architecture and microarchitecture superscalar processor	1	2001	A high-speed dynamic instruction scheduling scheme for superscalar processors · MICRO 2001

Methods — techniques the papers use, named apart from their topics

dynamic scheduling scheme · 0.0

Year	Publication	Venue	Position
2001	A high-speed dynamic instruction scheduling scheme for superscalar processors Masahiro Goshima, Kengo Nishino, Toshiaki Kitamura, Yasuhiko Nakashima, Shinji Tomita, Shin-ichiro Mori	MICRO	2