Dan Cao

dblp:95/7129 · DBLP profile ↗
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4ranked-venue papers
1as first author
2since 2021 · last 2025
—ORCID · conflict

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3 · 1 first-author · 1 since 2021Graphics, computer vision, multimedia, augmented reality and games · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Artificial intelligence
1 paper
3D vision · 87% Vision and language · 13%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Computer vision › 3D vision
3d human pose estimation
0.912025
Language-Driven 3D Human Pose Estimation in Multi-Person Scenarios: A New Dataset and Approach · ACM Multimedia 2025
Computer vision › 3D vision › 3d human pose estimation
multi-person 3d pose estimation
0.912025
Language-Driven 3D Human Pose Estimation in Multi-Person Scenarios: A New Dataset and Approach · ACM Multimedia 2025
Computer vision › Vision and language › language-guided learning
language-guided vision
0.312025
Language-Driven 3D Human Pose Estimation in Multi-Person Scenarios: A New Dataset and Approach · ACM Multimedia 2025
YearPublicationVenuePosition
2025 Language-Driven 3D Human Pose Estimation in Multi-Person Scenarios: A New Dataset and Approach
Tingrui Shen, Bangzhen Liu, Zhirun Fan, Shiting Zhang, Dan Cao, Shengfeng He
ACM Multimedia7
2022 3D genome assisted protein-protein interaction prediction
Zehua Guo 0004, Liangjie Liu, Mofan Feng, Runqiu Chi, Xianbin Su, Luming Meng, Dan Cao, Guang He, Yi Shi 0007
Future Gener. Comput. Syst.13
2014 ePASS: An expressive attribute-based signature scheme with privacy and an unforgeability guarantee for the Internet of Things
Jinshu Su, Dan Cao, Baokang Zhao, Xiaofeng Wang 0002, Ilsun You
Future Gener. Comput. Syst.2
2009 A multi-task-oriented security processing architecture with powerful extensibility
abstract
A multi-task-oriented security processing architecture is presented in this paper. This architecture contains a host microprocessor and multiple security processors (SP). The SP could integrate dedicated Crypto-Engines, which provides functional extensibility. And the performance scalability and multi-task parallelism could be enhanced by increasing the number of SPs on system bus. It's demonstrated that this architecture greatly improves the system efficiency. A test chip is implemented based on SMIC 0.18 um standard CMOS technology, and its functionality is well verified.
Dan Cao, Jun Han 0003, Xiaoyang Zeng, Shi-ting Lu
ASP-DAC1