Jiayang Li 0002

dblp:95/7674-2 · DBLP profile ↗
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5ranked-venue papers
3as first author
5since 2021 · last 2026
0009-0004-3826-5845ORCID · conflict

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 5 · 3 first-author · 5 since 2021
YearPublicationVenuePosition
2026 A Clock-Independent, Time-Domain Rapid Calibration Method for Memristor-based Analog Computing AI Processors
abstract
Memristor-based analog computing shows promising energy efficiency compared to digital counterparts. High- performance memristor-based AI processor has multi-level memristors, combined with the effect of device retention and ageing, the memristor readout system has tight readout margin to accurately determining the state of the memristor. Because the accuracy of the readout comparator determines the maximum accuracy the system can achieve. To address this, we proposed a high precision, clock-independent offset calibration scheme. The calibration scheme uses edge-triggered pulse-based calibration signal that makes the calibration accuracy independent of clock speed. The coarse-fine calibration steps are used to rapidly converge to minimum offset with high precision. A built-in digital calibration flag indicates the calibration status, that enables the synchronisation across arrays of comparators to facilitate scaling. The comparator is designed, laid out and simulated using 12 nm FinFET process. The comparator achieves average input voltage offset of 120 μV with 50 μV standard deviation after calibration, while the conventional method has the offset of 1.35 mV with standard deviation of 390 μV.
Matthew Schormans, Zhiqiang Que, Dinesh Pamunuwa, Jiayang Li 0002
ISCAS5
2025 A 2.43 mW Multi-frequency Electrical Impedance Tomography ASIC with Dual-Mode Impedance Readout
abstract
This paper presents a multi-frequency time-variance-based Electrical Impedance Tomography (EIT) ASIC, designed to balance high-speed performance with low power consumption for biomedical applications. The ASIC leverages a dual-mode impedance readout architecture, incorporating time-to-digital demodulation at high frequencies and digital I-Q demodulation at low frequencies, which together address limitations in conventional EIT systems regarding data acquisition speed and power efficiency. The proposed system includes a current generator with an integrated auto-calibration scheme and a flexible clock generator with multiple PLLs, supporting a wide frequency range from 15.6 kHz to 1 MHz. Fabricated in a 65 nm CMOS process, the ASIC achieves a total power consumption of 2.43 mW and enables detailed multi-frequency impedance analysis while maintaining compactness and cost-effectiveness. In-vitro measurements with water tank validate its efficacy in different frequency-dependent impedance changes.
Jiayang Li 0002, Dai Jiang, Andreas Demosthenous
ISCAS1
2025 Design and Optimization of a High Linearity On-Chip Sinusoidal Current Generator for Bioimpedance Measurements Using Direct Digital Synthesis
abstract
This paper presents an optimization methodology to enhance the linearity of direct digital synthesis (DDS)-based on-chip sinusoidal current generators (SCGs) for bioimpedance measurements. After a detailed analysis of the origin of harmonics and their impact on measurement accuracy in conventional DDS-based SCGs, three different harmonic cancellation schemes are proposed. These are designed to decrease the harmonics in various applications with differing hardware requirements, significantly improving the precision and efficiency of DDS-based SCGs. The approach was implemented in a DDS-based SCG in 65 nm CMOS technology. Both simulations and measurements demonstrate a marked improvement in linearity with a figure-of-merit at least 9.4 times better than prior work. Although tailored for bioimpedance applications, the approach is also suitable for other low power, high linearity sinusoidal signal generators.
Jiayang Li 0002, Dai Jiang, Andreas Demosthenous
IEEE Trans. Circuits Syst. I Regul. Pap.1
2024 A Current DAC Based Current Generator with Fourth-Order Current-Mode Filter for Electrical Impedance Tomography
abstract
The current generator is one of the most essential parts in electrical impedance tomography (EIT) systems. State-of-art current generators suffer from the trade-off between current efficiency, linearity, output impedance and well-controlled output current level. To address these challenges, a current DAC based current generator with a fourth-order current-mode filter is proposed. The current generator was designed and simulated in a 65 nm CMOS process. By utilizing the proposed current-mode filter and the master and slave current DAC, the current generator achieves a well-controlled output current leveling with 255 tunning steps, 83.9% current efficiency, 0.11% THD at 1 mAppoutput current and 2 MΩ output impedance at 500 kHz.
Jiayang Li 0002, Yu Wu 0007, Dai Jiang, Richard H. Bayford, Andreas Demosthenous
ISCAS1
2024 Three Coils, High-Resolution Receiver Positioning System for Wireless Power Transfer
abstract
Wireless power transfer with inductively coupled coils is widely used for powering implantable devices. For a continuously moving receiver coil (Rx), real-time detection of its position is important for the magnetic field distribution control. This paper proposes an Rx positioning system that uses three varying-pitch coils and applies a trilateration algorithm for positioning. It operates at a frequency of 125 kHz. The detection area is approximately 224 cm2, when using a 2 cm radius Rx. Experimental results show the position detection system has a 1 cm2resolution with an average deviation of 6.8 mm.
Jiayang Li 0002, Dai Jiang, Andreas Demosthenous
ISCAS2