This paper analyzes the rate-matching algorithms for LDPC codes in 5G New Radio (NR) framework. Key features of NR LDPC rate-matching design includes flexible bit-selection based on circular buffer operation, enhanced decoding latency via code construction based on a single-parity-check extension from a high rate code, systematic bit puncturing, and support for limited buffer rate-matching (LBRM). IR-HARQ is supported via several redundancy versions (RVs) defined non-uniformly over the transmit circular buffer, enabling possibility of multiple self-decodable RVs. This paper, discusses NR LDPC structure, design, and its key features, followed by an in-depth investigation of IR-HARQ functionality, rate-matching, and (re-)transmissions via different RV ordering selections. Performance of single transmissions, as well as re-transmissions using different schemes are studied and evaluated using throughput and BLER metrics. This study attests the flexibility and robustness of NR LDPC design in addition to efficient support of IR-HARQ operation.

Relays are being proposed as key technology elements for LTE-Advanced (LTE-A). This paper shows that throughput gains of using relays in a cellular network (relative to a network without relays) are highly dependent on relay coverage which is defined as the percentage of users served by relays. System-level simulations and analysis is used to illustrate the impact of relay coverage on throughput performance. Techniques to further improve the performance gains are proposed.

This paper discusses circular buffer rate matching (CBRM) algorithms for the turbo code in the long term evolution (LTE) of the WCDMA-based air interface. To enhance performance at high code rates, systematic bit puncturing is incorporated in conjunction with the CBRM. The RM algorithm is further optimized based on the algebraic properties of the QPP interleavers and the 8-state recursive systematic convolutional code of the LTE turbo code.

The Long Term Evolution (LTE) of the WCDMA standard requires turbo decoding throughputs of up to 100 Mbps. Unfortunately, the existing WCDMA turbo interleaver does not permit an efficient high throughput implementation. The almost regular permutation (ARP) and quadratic polynomial permutation (QPP) interleavers were proposed to rectify this situation with QPP selected for LTE. In this paper, the interleavers are compared and a full suite of LTE designs and performance results for both are presented.

This paper presents a low-complexity interleaver design that facilitates the high throughput turbo decoding required for next generation wireless systems. Specifically, it addresses the interleaver design issues that arise when several Log-MAP processors are used in parallel to improve turbo decoding throughput. In such a parallel decoder, memory access contentions occur when more than one extrinsic value is to be written to or read from the same memory block at the same time. These contentions may be avoided by designing contention- free (CF) interleavers that incorporate hardware constraints into the interleaver description. The paper first derives bounds on the number of CF interleavers, demonstrating that the fraction of interleavers of a given size that are contention-free is quite small. In spite of this, a class of contention-free "inter-window shuffle" (IWS) interleavers are shown via simulation to achieve near-WCDMA performance. Further, the paper shows that the memory requirement of CF IWS interleavers is small compared to an alternate contention-resolving method that uses a modified memory addressing scheme. Finally, we note that the advantages of contention-free interleavers have led to the adoption of a CF quadratic permutation polynomial (QPP) interleaver in the 3 GPP long term evolution (LTE) standard.

This paper presents a high-speed "turbo-like" decoding algorithm for certain structured LDPC codes such as those adopted in IEEE 802.16e and in the draft 802.11n standards. It is shown that after a key modification, such LDPC codes may be processed as generalized repeat accumulate codes, codes which are known to support "turbo-like" decoding. A GRA-like encoder of structured LDPC codes is derived, which in turn leads to the decoding algorithm. It is also shown that the "structured" properties result in an inherent parallelism, leading to an efficient high speed decoder implementation

Interleavers that avoid memory contentions in parallelized log-MAP decoding are analyzed and designed. Bounds are derived demonstrating that the fraction of interleavers that are contention-free is small. Nevertheless, contention-free "inter-window shuffle" interleavers with a simple implementation and reasonable memory requirements are shown to surpass 3GPP performance.