Computational-In-Memory (CIM) is an energy-efficient paradigm that integrates computation directly within memory arrays, reducing the bottleneck associated with data transfer. This approach is beneficial for Artificial Intelligence (AI) applications that require on-chip learning for real-time processing. However, implementing on-chip learning in CIM architectures remains challenging due to limited throughput and energy-efficiency during both online training and inference. In conventional architectures, weight updates necessitate the inference process to halt to avoid unintended computation outcomes. To overcome this limitation, this paper presents a novel Spin-Orbit Torque (SOT)-based CIM architecture tailored for continuous on-chip learning applications, which enable weight updates without interrupting the inference. The proposed SOT bit-cell utilizes two read ports and one write port (2R1W) configuration, where one read port (1R) is dedicated to inference and one read and one write (1R1W) for on-chip learning that enables concurrent read and write operations. Our proposed architecture is evaluated at the system-level using the Generic-PDK 45 nm technology node, demonstrating 2.4× improvement in energy-efficiency and 5.4× improvement in throughput compared to state-of-the-art solutions, with minimal overhead.

This paper presents a novel linear regression-based polynomial chaos (PC) approach for the efficient multidimensional uncertainty quantification of general distributed and lumped high-speed circuit networks. The key feature of this paper is the development of a modified Fedorov search algorithm based on the D -optimal criterion that expeditiously locates a highly sparse set of nodes within the multidimensional random space where the original network needs to be probed. Specifically, the number of selected nodes is kept equal to the number of unknown PC coefficients of the network response, thereby making this approach substantially more efficient than the conventional linear regression approach which is based on an oversampling methodology. Additionally, due to the D -optimal criterion, this approach ensures highly accurate recovery of the PC coefficients. The validity of this paper is established through multiple numerical examples.

This paper presents a numerical convolution based approach for transient simulation of distributed networks characterized by band limited frequency domain data when terminated with arbitrary nonlinear circuits. The proposed algorithm uses time-frequency decompositions to extract multiple propagation delays of a distributed network and the associated attenuation losses in a piecewise manner, and implements inverse fast Fourier transform to efficiently convert the frequency response into a sum of delayed time domain responses. Numerical examples illustrate that the proposed algorithm shows significantly more accurate results for networks with multiple long delays when compared to existing numerical convolution techniques.

This paper presents a delay and crosstalk noise model for coupled resistance-inductance-capacitance (RLC) on-chip interconnects. The proposed algorithm, based on a modified Lie formula, is used to convert the solution of the transmission line network into delay algebraic equations to obtain the time domain response. The proposed algorithm is not limited to fixed number of coupled RLC lines or to specific topologies and can be used to model both identical and nonidentical multiconductor lines and loads. For the example presented in this paper, the 50% delay and crosstalk using the proposed method agrees with SPICE results to within 0.75% average error.

In this paper, a closed-form matrix rational-approximation algorithm is proposed to efficiently model the delay and crosstalk noise of coupled RLC on-chip interconnects. A key feature of the proposed algorithm is that, for any rational order, the approximation is obtained analytically in terms of predetermined coefficients and the per-unit-length parameters. As a result, the proposed method is not limited to fixed number of poles and provides a mechanism to increase the accuracy for cases when inductive effects are significant, the length of the line increases, or when the rise time of the signal becomes sharper. An error criterion is provided to select the order of approximation. The algorithm is tested for various single- and coupled-interconnect scenarios. The 50% delay and overshoot results match that of SPICE with less than 2% average error. The crosstalk results also accurately match those of SPICE with less than 4% average error.