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Homer H. M. Chern

dblp:96/1096 · DBLP profile ↗
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2ranked-venue papers
0as first author
0since 2021 · last 1996
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1Graphics, computer vision, multimedia, augmented reality and games · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Integrated circuit design · 100%

Topics — the 2 heaviest of 2, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Integrated circuit design › digital arithmetic circuits
CORDIC
0.011996
A Novel Implementation of CORDIC Algorithm Using Backward Angle Recoding (BAR) · IEEE Trans. Computers 1996
Integrated circuit design
digital circuit design
0.011996
A Novel Implementation of CORDIC Algorithm Using Backward Angle Recoding (BAR) · IEEE Trans. Computers 1996

Methods — techniques the papers use, named apart from their topics

constant scaling factor · 0.0backward angle recoding · 0.0
YearPublicationVenuePosition
1996 A Novel Implementation of CORDIC Algorithm Using Backward Angle Recoding (BAR)
abstract
We propose a backward angle recoding (BAR) method to eliminate redundant CORDIC elementary rotations and hence expedite the CORDIC rotation computation. We prove that for each of the linear, circular, and hyperbolic CORDIC rotations, the use of BAR guarantees more than 50% reduction of elementary CORDIC rotations provided the scaling factor needs not be kept constant. The proposed BAR algorithm is simple, and amenable to VLSI implementation. Taking practical applications into consideration, we discuss how to incorporate convergence range enhancement procedure with BAR, and how easy it is to devise a constant-scaling-factor BAR algorithm while still enjoying 25% reduction of CORDIC elementary rotations.
Yu Hen Hu, Homer H. M. Chern
IEEE Trans. Computers2
1990 An efficient VLSI CORDIC array structure implementation of Toeplitz eigensystem solvers
abstract
A novel, efficient implementation of the Toeplitz eigensystem solver using a doubly pipelined VLSI CORDIC array processor is presented. First, a backward CORDIC angle recoding scheme is proposed which is able to reduce the number of internal CORDIC iterations by at least 50%. It is shown how to apply this scheme to a family of feedforward algorithms for solving general linear systems, especially the Toeplitz systems. This leads to the implementation of a Toeplitz eigensystem solver with CORDIC-based array processors.>
Yu Hen Hu, Homer H. M. Chern
ICASSP2