Realtime video streaming is one of the most important tool for the computer supported collaborative workspace (CSCW). CSCW requires bi-directional or many-directional video exchanging. The delay or jitter caused by network quality is easily affecting application or users of CSCW. The quality of experience (QoE) of CSCW with video streaming over IP networks depends on the quality of network. It is important to consider the relationship between the QoE of video streaming and quality of service (QoS) of the network in order to achieve high quality CSCW services effectively. Then we can define the suitable parameter of networks for the applications. The goal of this research is to establish the evaluation method of the correlations between the QoE of CSCWs and QoS of networks to obtain the optimal real-time communication system design. In this paper, we propose a method to measure the correlation between the application and network QoS with precise packet monitoring environment. The result shows that micro-second resolution helps a lot to capture the precise behavior which effects the codec system's performance.

This paper proposes a novel IP multihoming scheme in which fast packet processing nodes switch and distribute the traffic on an application flow basis. The newly developed node, called A-BOX, classifies each incoming packet up to the layer 4(L4) or L7(payload) header, edits it as necessary, and forwards it to an outgoing port according to the header's entry. The NAT-like sandwiched path formed between A-BOXs acts like one path defined for an application flow, and so suits applications that have QoS(quality of service) requirements. A-BOX realizes wire rate forwarding by applying hardware techniques including FPGAs. A-BOX can measure the traffic on a real time basis for each flow and distribute the flow to achieve the application's requirements. The software interface of A-BOX means that the network can be transparently controlled for each application flow. We clarify the feasibility of A-BOX's basic methods, which include network condition monitoring via individual flow with huge background traffic, switching a specified flow in the multihoming condition, and traffic sharing/bandwidth aggregation.

An active network node architecture, called Active Packet Editing (APE), is proposed. The main concept of APE is to accelerate functions essential to active network operation, such as packet classification and NAT (Network Address Translation). The twofold architecture of APE combines a software active packet processor with a high-speed hardware packet editor. Based on preset rules (pattern, action), the packet editor classifies and modifies packets passing through the node. Upon the receipt of active packets, the software active packet processor dynamically configures the packet editor. This paper focuses on introducing the high-speed packet editing mechanism which utilizes FPGAs (Field Programmable Gate Arrays) and CAMs (Content Addressable Memories). A prototype network node based on the architecture performs Gigabit-class throughput with packet editing.

We developed a flexible network node that is tuned for high-speed and multilayer packet manipulation. The key idea is a dynamic function assignment mechanism; each packet processing task is assigned to several processing modules in an on-the-fly manner and incoming packets are processed in them. With this mechanism, we can freely arrange the modules and add extra ones if more processing power is needed. In addition, the processing modules are realized using field programmable gate arrays (FPGAs) and micro processing units (MPUs). Thus, the functionality of each module can be dynamically changed at anytime. In this paper, the system concept and its implementation are described with an example application.

The paper describes the concept and implementation of a telecom emulator that features both reconfigurability and high-speed processing. The emulator can be easily transmuted into any telecom system as a real node. It has two innovative system design concepts. The first is to divide the specification into simplified processes based on the open system interconnection (OSI) reference model. The second is the use of a sophisticated hardmacro and its software-callable driver. We implemented a prototype system called ATTRACTOR and applied it to some telecom applications. The applications were able to be implemented in a short design time and were operated in real computer network environments.

A novel distributed-resource abstraction environment is introduced. You can access any resource in a computer network as a memory mapped I/O device, as if it was attached to the local bus of your PC. This network technology gives us several benefits. From the application development viewpoint, no network-related programming is required, and we don't need to modify the applications even if the network topologies and protocols are changed. On the other hand, network maintenance and upgrading can be done anytime without worrying about the application users, because the environment completely separates or hides the network from the applications. The API (Application Program Interface), a resource abstraction mechanism, and a directory service are implemented. In addition, a reconfigurable hardware technology is adopted to perform autonomous network control using a lour layer protocol. Furthermore, we introduce a testbed that allows heterogeneous resources to be utilized, and demonstrate the feasibility of our concept using some applications.

This paper describes a project dedicated to developing an improved (in terms of usability) version of our previous telecommunication-oriented field programmable gate array (FPGA), and its applications. To achieve this goal, we adopt several challenging design strategies. First, we determine the new FPGA architecture based on a quantitative evaluation carried out to optimize the interaction between the FPGA and CAD algorithms. In addition, we create a new chip design environment that allows semi-automatic test pattern generation and cross-checking between logic and layout design. Furthermore, a dedicated CAD system is developed based on a consideration of the evaluation results and the characteristics of the FPGA. As a result of these design strategies, the FPGA and CAD system are well-balanced, and even though the FPGA has very rich routing resources, the routing process can be finished quickly without sacrificing application-circuit performance. The FPGA is applied to several reconfigurable systems for telecommunications, and is found to offer the required functions and good performance.

The paper describes a transmutable telecom system called ATTRACTOR, which uses more than 100 FPGAs, and features both reconfigurability and high performance. There are two key innovations. One is the board-level modularity concept that allows different functions to be implemented on different boards individually. The other is a high-speed serial link mechanism that provides excellent inter-board communication without sacrificing performance. Thus this system can be completely reconstructed to suit different applications by arranging different board combinations and reconfiguring each board. Using ATTRACTOR, we realized an IP packet forwarder, which is very speed-intensive telecom function, that has to decide the next-hop address of each incoming IP packet and send it out on-the-fly. It was confirmed that the function works well in a real ATM-LAN environment.

No abstract available.

We have developed an architecture-oriented routing method for a telecommunications FPGA (Field-Programmable Gate Array) which has rich hierarchical routing resources. Our routing method consists of four routing procedures, each of which are related to a specific part of the routing resource architecture of the FPGA. It can accomplish routing results almost five times faster than a reference method that does not consider the routing resource architecture. The key idea in our approach is to reduce the number of possible resource candidates by referring to both the logical net structure and the FPGA resource architecture. We apply different routing algorithms according to the amount and architecture of candidate routing resources. Experiments show that our architecture-oriented method is more effective than conventional single-algorithm-based methods.

In designing FPGAs, it is important to achiev e a good balance bet w een the number of logic blocks, suc h has Look-Up Tables (LUTs), and wiring resources. It is difficult to find an optimal solution. In this paper, w e presen t an FPGA design methodology to efficiently find well-balanced FPGA architectures. The method covers all aspects of FPGA development from the architecture-decision process to physical implementation. It has been used to develop a new FPGA that can implement circuits that are twice as large as those implementable with the previous version but with half the number of logic blocks. This indicates that the methodology is effectiv e in dev eloping well-balanced FPGAs.