Logic encryption is a popular technique to safeguard an IC design from different security vulnerabilities. However, several recently proposed attacks can extract the secret keys of an encrypted design. In this paper, we propose a new logic encryption strategy, which integrates an additional key generation unit with the design. The key generation unit takes external keys and performs a permutation of the keys to generate a highly interdependent key-set, which are applied to the inputs of the keygates. Experimentation on IWLS'05 benchmarks shows that our proposed strategy can thwart most of the existing attacks, thus enhances the security of logic encryption at the cost of reasonable design overheads.

Diagnosing chain failures is extremely important to ramp up production yield. Use of modern day low pin compressors limit the observability making chain diagnosis a difficult problem. When multiple chains fail during initial ramp up of yield, the high-resolution patterns are generally used for diagnosis. These patterns are generated using special ATPG settings and are very high in numbers. These high-resolution patterns burden the Automatic Test Equipment (ATE) with extra test time and test memory. In this work, we have developed a new algorithm to diagnose multiple chains using compressed production test pattern set. We believe that this is the first work which exhibits the use of production patterns to diagnose multiple chains. Diagnosing one chain at a time, this algorithm applies the information obtained so far to diagnose other chains. Experimental results show that up to 10 chains can be diagnosed simultaneously using compressed production patterns.

Diagnosis with a modern day low pin convolution compressor is difficult. Generally, it is done in two steps. In the first step, known as failure mapping, failures are mapped to the scan cells from the faulty responses recorded at compressor outputs on the Automatic Test Equipment (ATE). In the second step, normal scan diagnosis - cone tracing and fault simulation - is used to identify the faulty gate/pin/net. Accurate failure mapping is extremely important for successful diagnosis. Unfortunately, due to aliasing and presence of don't cares in the response, no mapping algorithm can guarantee that mapping will always be correct for convolution compressors. In this paper, we proposes a new technique which can handle incorrect mappings (the first step of diagnosis). This feature is shown to provide significant improvement over previous methods. Combining the new proposed techniques to the prior algorithms, we have achieved scan level diagnosis accuracy (99.8%) in a compression environment with extreme low pin compressors.

Diagnosis is extremely important to ramp up the yield during the integrated circuit manufacturing process. It reduces the time to market and product cost. Limited observability due to test response compaction negatively affects the diagnosis procedure. When multiple chains, mapped to a single compactor, fail, diagnosis becomes extremely difficult. The procedure is even more complicated because when a circuit fails the flush test, not all the patterns are applied. Only a few of the patterns are applied and the observed responses are used to diagnose the faulty chains. In this paper, we have proposed an efficient masking strategy that will be very useful for diagnosis of scan chains when multiple scan chains fail. The proposed strategy uses the redundancy in fault detection by the test patterns and masks scan chains in such a way that enough information can be provided with small increase in test pattern count. A new tester architecture that will select and apply only those patterns having enough information for diagnosis has also been proposed. Diagnostic resolution and first hit index achieved by our method are very close to their ideal values, which validate the applicability of our approach.

Scan Compression has become the default design-for-test (DFT) methodology for achieving high quality test at lower costs. Just as scan matured over a span of 40 years we are now observing Scan Compression improving and adapting to the needs of current designs. In this paper we present an industrial case study demonstrating how the DFT flows are impacted in the presence of compression logic for test. We develop various DFT architectures using the zScan compression technology and discuss the pros and cons of each flow w.r.t. Pin limited test and modular DFT insertion. We also show that the decisions of pin count and scan chain count dramatically impact the final QoR i.e., Test application time and test data volume required to test the chip.

This talk will cover different aspects of low-cost and high-quality SOC test to meet varying end application requirements (catalog, automotive, wireless, etc.). While some of the test techniques are well-known, they will be stitched together through illustrations to indicate how test cost can be minimised in the presence of various design and tester constraints, without compromising on the quality. Different digital and analog IP components will be considered as part of the SOC test integration process

This brief proposes a framework to analyze multiple faults based on multiple fault simulation in a particle swarm optimization environment. Experimentation shows that up to ten faults can be diagnosed in a reasonable time. However, the scheme does not put any restriction on the number of simultaneous faults.

Volume Diagnosis is extremely important to ramp up the yield during the IC manufacturing process. Limited observability due to test response compaction negatively affects the diagnosis procedure. Hence, in a compaction environment, it is important to implement Design For Diagnosis (DFD) methodology to restore diagnostic resolution. In this paper, a novel DFD technique which makes the faulty chains to behave as good chains during loading, has been proposed. As a result, the errors introduced in the responses, must occur during unloading of the scan chains. Diagnosis can then be performed by directly comparing the actual and expected responses without any fault simulation - leading to significant reduction in time. Results on benchmark circuits show that the average number of suspected cells for single chain failure is 1.27 (ideal value being 1) and the time taken for diagnosis is in the order of milli-seconds.

When multiple chains, mapped to the same compactor output fail, AND-gate masking logic at the compactor side can be used to aid in diagnosis. The basic idea is: if for some pattern, only one faulty chain is observed and all the other faulty chains are masked, then the corresponding compacted response will only be affected by the non-masked faulty chain. Such a test pattern will help to diagnose that chain.

This paper introduces a new metric to characterize test sets in terms of their diagnostic power. Our method uses much less space compared to the existing ones and is quite accurate. The metric can be utilized to increase the diagnosability of incompletely specified test sets via don't care filling. The X-filling approach can be integrated with test pattern generation tools to aid in better diagnostic pattern set generation.

Scan compression technology innovation has broken out into solving the data volume problem keeping the test application time gains relatively constant over the generations of technologies. While data volume reductions are important there is a need to take the test application time gains to the next level as it has a direct impact to the cost of test. In this paper an enhancement to combinational compression is described that relies on increasing the encoding bandwidth for aggressive test application time targets. An architecture is described that adds very little area overhead to a combinational compression architecture by reusing the internal scan chains of the design for encoding bandwidth for a set of the test patterns.

Scan compression technology is essentially IP that provides an interface between the scan-inputs/outputs and the internal scan chains. The IP configuration that is put into the design is based upon some user specified constraints that are related to the target compression and the available scan terminals. The configuration selected may or may not be the best suited for the design it is inserted in. Usually the compression IP can be configured in many different ways. Some configurations are better suited for particular designs than others. If one were able to predict the configuration of the compression IP to match the needs of the design then one would expect the best results from the compression technology. In this paper we describe a method to predict the optimum IP configuration for Adaptive Scan, which is a specific type of compression technology. The concepts and methodology discussed here are applicable to any compression scheme.

Power dissipation of an LSI circuit during scan testing, especially at-speed scan testing, can be several times higher than that during functional operations. Excessive test power causes hot spots and/or severe IR drop that may lead to chip damage, undue yield loss, or reliability degradation, especially for low-power LSI circuits. As a result, it is becoming increasingly important to reduce test power by lowering test-induced toggle activity in order to make scan test “power-safe”. However, with the stress on reducing toggle activity during scan test one might question: Have we gone too far? Should we reduce toggle activity below functional levels? Should we even plan for many test sets with different toggle activities? Can the test power problem be solved by existing DFT and ATPG solutions? What's missing in today's solutions? What's next for low-power testing? This panel provides an interactive forum to discuss these critical questions with industry experts from both semiconductor and EDA companies. It helps practitioners and researchers alike in their quest for more effective and more efficient solutions to the test power problem.

Scan compression has emerged as the most successful solution to solve the problem of rising manufacturing test cost. Compression technology is not hierarchical in nature. Hierarchical implementations need test access mechanisms that keep the isolation between the different tests applied through the different compressors and decompressors. In this paper we discuss a test access mechanism for Adaptive Scan that addresses the problem of reducing test data and test application time in a hierarchical and low pin count environment. An active test access mechanism is used that becomes part of the compression schemes and unifies the test data for multiple CODEC implementations. Thus, allowing for hierarchical DFT implementations with flat ATPG.

The use of scan based compression techniques is becoming mandatory on current designs. While high compression is desired to hold the test costs within limits, it is important to understand the bounds set by the entropy of the care bits required by different compression techniques, to enable the selection of the right set of design and test parameters. This paper highlights the available solution space for compression based designs and discusses the various parameters which result in test tradeoffs. The discussion is supported with elaborate experimental data. Through them, the paper offers an insight into the solution space of compression techniques and makes resulting recommendations.

Scan compression technology combines the expected responses from multiple scan chains to be observed at fewer scan outputs. As a result unknowns (Xs) in the test response interfere with the good values that could be observed. Prior to this paper, Xs in the test response were treated as bad for compression and solutions either removed, bypassed, or blocked the Xs from interfering with the other responses. In this paper we show that some X scan be added to improve test compression quality of results. The trade-off between improved observability due to simultaneous clocking of interacting clock domains is played against the reduced observability caused by the Xs in the response due to race conditions. In this paper we show that when the inter clock domain Xs are added but limited, the gains achieved by adding the Xs far exceeds the losses in bringing together the Xs with other observes in scan compression.

We present low power illinois scan architecture (LPILS) to achieve power dissipation and test data volume reduction, simultaneously. By using the proposed scan architecture, dynamic power dissipation during scan testing in registers and combinational cells can be significantly reduced without modifying the clock tree of the design. The proposed architecture is independent of the ATPG patterns and imposes a very small combinational area penalty due to the logic added between the scan cells and the CUT. Experimental results for two industrial circuits show that we can simultaneously achieve up to 47% reduction in dynamic power dissipation due to switching and 10X test data volume reduction with LPILS over basic scan.

Average and peak power dissipation can be reduced by controlling the switching activity in the scan chains during shift and capture cycles. In particular, minimum transition count or adjacent fill algorithm reduces transitions in the scan chains and has been shown to reduce average power dissipation during shift. In this paper, we show via statistical analysis of industrial circuits that contrary to conventional belief, scan-in and scan-out vectors are highly correlated for adjacent fill vectors. We also show that this correlation can be used to control the switching activity during the capture cycle. We propose a new filling algorithm called bounded adjacent fill that generates test vectors with low shift and capture switching activity and with no impact on pattern count.

Testing today of a several hundred million transistor system-on-chip with analog, RF blocks, many processor cores and tens of memories is a huge task. What the test technology be like in year 2020 with hundreds of billions of transistors on a single chip? Can we get there with tweaks to today's technology? While the exact nature of the circuit styles, architectural innovations and product innovations in year 2020 are highly speculative at this point, we examine the impact of likely design and process technology trends on testing methods

Testing for small delay defects requires ATPG-FS tools to understand timing information of the design such that transition delay faults can be detected along longer paths. In this paper, timing information is analyzed for use in test automation tools to test for small delay defects. Fundamentals of static timing analysis are analyzed with regard to test. This paper concludes that Signal Integrity information can be ignored by test automation tools when timing information is used to guide ATPG tools towards longer paths. This paper also shows that a lack of understanding of clock trees in the long path ATPG algorithm leads to incorrect results.

The authors present a novel DFT technique based on multimode Illinois scan architecture (MILS) for low pin count test that simultaneously reduces test data volume and test application time. By using the proposed technique, significant savings in test data volume, and testing time can be obtained without modifying the clock tree of the design and with a very small combinational area overhead. Experimental results for two large industrial circuits show that the test data volume and test application time reduction of the order of 100times can be achieved in all cases with less than 1% area overhead over ILS.

Scan is widely accepted as the basis for reducing test cost and improving quality, however its effectiveness is compromised by increasingly complex designs and fault models that can result in high scan data volume and application time. The authors present a scan compression method designed for minimal impact in all aspects: area overhead, timing, and design flow. Easily adopted on top of existing scan designs, the method is fully integrated in the scan synthesis and test generation flows. Data and test time compressions of over 10times were obtained on industrial designs with negligible overhead and no impact on schedule.

Before on-chip scan compression, it was possible to use different EDA tool vendors to do scan insertion, pattern generation, and diagnosis. On-chip scan compression changed that use model since each tool vendor supplied a different type of scan compression logic and had tool-specific ways to pass necessary information from scan insertion to pattern generation and from pattern generation to diagnosis. OCI (open compression interface) is a standardization of how the necessary data is passed from test logic insertion to pattern generation to diagnosis such that different vendors can be used for each step independent of the on-chip scan compression logic used. This document discusses the need for OCI and gives a conceptual overview of the OCI standard

ITC has organized an expert quiz panel comprised of the following experts: R. Aitken; A. Crouch; J. Patel; and T.W. Williams. E.J. McCluskey, the moderator, presents to the two teams of panelists a series of simple questions designed to reveal the panelists test domain knowledge. The topics include state of the art test technology issues such as compression, timing tests, new fault models, ATPG issues, standards, process variation, DFM-test and N-detect

Recent test-cost reduction methods are based on controlling the initial state (seed) of a pseudo-random pattern generator (PRPG) so that deterministic values are loaded in selected scan cells. Combined with an unload-data compression technique, PRPG seeding reduces test data volume and application time. This paper presents a method of mapping each scan load to multiple PRPG seeds, computed so that test pattern count, data volume, and, therefore, test cost are minimized. This method also allows smaller and fewer PRPGs, reducing the area overhead of test-compression circuitry. The results on deep-submicron industrial designs, show significant test cost reduction when this method is applied with either X-tolerant or X-free unload-data compression

Scan technology does not provides controllability and observability in the IC, which could ease IP theft. Hence it is necessary not to eliminate scan chains but to add security to design-for-test (DFT) as a design constraint. Scan chains with decryption and encryption technology allow for scan chains to be used in security sensitive situations. Scan chains and hence high-quality test are implemented on ICs without compromising the IP on the chip.

This paper extends the reconfigurable shared scan-in architecture (RSSA) to provide additional ability to change values on the scan configuration signals (scan enable signals) during the scan operation on a per-shift basis. We show that the extra flexibility of reconfiguring the scan chains every shift cycle reduces the number of different configurations required by RSSA while keeping test coverage the same. In addition a simpler analysis can be used to construct the scan chains. This is the first paper of its kind that treats the scan enable signal as a test data signal during the scan operation of a test pattern. Results are presented on some ISCAS as well as industrial circuits.

In this paper, an efficient technique for test data volume reduction based on the shared scan-in (Illinois Scan) architecture and the scan chain reconfiguration (Dynamic Scan) architecture is defined. The composite architecture is created with analysis that relies on the compatibility relation of scan chains. Topological analysis and compatibility analysis are used to maximize gains in test data volume and test application time. The goal of the proposed synthesis procedure is to test all detectable faults in broadcast test mode using minimum scan-chain configurations. As a result, more aggressive sharing of scan inputs can be applied for test data volume and test application time reduction. The experimental results demonstrate the efficiency of the proposed architecture for real-industrial circuits.

In this paper the solution the industry is driving towards for manufacturing test of SoCs is described. The quality of test for every core that is integrated on the chip is very important to the overall quality of the SoC. In this paper a method for evaluating the quality needs of an embedded core relative to the embedded environment is presented. Due to the partitioning of the test data and the increased stress in quality for individual designs the test application time is increasing. This paper presents the problems associated with test application time with SoCs.

In conventional delay testing, the test clock is a single pre-defined parameter that is often set to be the same as the system clock. This paper discusses the potential of enhancing test efficiency by using multiple clock frequencies. The intuition behind our work is that for a given set of AC delay patterns, a carefully-selected, tighter clock would result in higher effectiveness to screen out the potential defective chips. Then, by using a smarter test clock scheme and combining with a second set of AC delay patterns, the overall quality of AC delay test can be enhanced while the cost of including the second pattern set can be minimized. We demonstrate these concepts through analysis and experiments using a statistical timing analysis framework with defect-injected simulation.

Logic BIST is about to become a more main stream test method for IC testing. In some flows when a failure is encountered the IC is diagnosed to determine the cause of the failure. Diagnosing fails in Logic BIST is significantly different from that in a stored pattern test methodology. The first step is to determine the failing pattern or interval among the many patterns that were applied. Today this involves a binary search of the tests that were applied with Logic BIST. In this paper we improve on this binary search strategy to reduce the time taken to isolate the failing patterns by orders of magnitude.

Solving a system of linear equations has been widely used to compute seeds for LFSR reseeding to compress test patterns. However, as chip size is growing, solving linear equations requires a large number of computations that is proportional to n3. This paper proposes a new scan chain architecture and algorithm so that the order of computation is proportional to the number of scan cells in a chip. The new architecture is a methodology change that does not require complex Design-For-Testability (DFT) as proposed in the previous techniques. Instead of solving linear equations, the proposed new seed computation algorithm topologically determines seeds for test vectors. The compression ratio might be slightly lower than the other approaches, but the proposed approach can handle larger designs in a reasonable amount of time. Computation analysis shows that, for 1 million scan cell design, if we assume it takes 1 msec for the proposed technique to compute seeds, it would take more than 14 minutes for other techniques that solve linear equations.

The industry's adoption of powerful design methodologies, such as physical synthesis, formal verification, and static timing analysis are speeding the implementation and verification of multi-million gate ASICs and systems-on-chip (SoC). As the design community moves to the complete adoption of a physical synthesis flow, it is becoming evident that test synthesis must be aware of layout issues and well integrated within physical design tools. By bringing in key physical functions into the front-end of the DFT/physical synthesis flow, the designer is able to successfully meet all design and testability goals, with minimum impact on timing closure. In this paper, we present a DFT synthesis flow tightly integrated within physical synthesis to achieve physically optimized scan designs. This flow describes new test technology which uses physical information to achieve optimal scan chain partitioning, timing-driven scan ordering and DFT driven placement to dramatically reduce routing congestion, and achieve a rapid and predictable timing closure.

In conventional delay testing, two types of tests, transition tests and path delay tests, are often considered. The test clock frequency is usually set to a single pre-determined parameter equal to the system clock. This paper discusses the potential of enhancing test effectiveness by using multiple test sets with multiple clock frequencies. The two intuitions motivating our analysis are 1) multiple test sets can deliver higher test quality than a single test set, and 2) for a given set of AC delay patterns, a carefully-selected, tighter clock would result in higher effectiveness to screen out potentially defective chips. Hence, by using multiple test sets, the overall quality of AC delay test can be enhanced, and by using multiple-clock schemes the cost of adding the additional pattern sets can be minimized. In this paper, we analyze the feasibility of this new delay test methodology with respect to different combinations of pattern sets and to different circuit characteristics. We discuss the pros and cons of multiple-clock schemes through analysis and experiments using a statistical delay evaluation and delay defect-injected framework.

As part of an industry wide effort the IEEE is in the process of standardizing the elements of test technology such that plug & play can be achieved when testing SoC designs. This standard under development is a language namely, Core Test Language (CTL), which is introduced in this paper. CTL describes all necessary information for test pattern reuse and the needs of test during system integration. CTL syntax and its link to STIL are explained with examples.

The industry is scrambling to prevent a potential explosion in nanometer technology test cost where the cost to test a device is closing in on the cost to manufacture it. Across the test industry, entire methodologies are being readdressed, tester costs are being scrutinized, and test vector count is being reduced. In this paper, a new concept is presented that allows for lowering the cost of test by utilizing the tester resources more efficiently. The solution presented brings together an existing concept of being able to reconfigure scan chains with methods that allow the same test pattern data to be applicable for all configurations. A data model is created to emphasize the use of such technology. The concepts developed in this paper are compatible with other test cost reduction methods.

Typically the DFT features are decided during the design and remain fixed after the design is completed. This makes a device testable only on ATEs, which can satisfy the test requirements for that chip. If such an ATE is not available then the IC either cannot be fully tested, or ATE resources are wasted when it is designed for less capabilities. This paper presents a methodology that builds on the tester retargetable pattern technology for testing ICs on testers with different pin capabilities. Such a capability would be an essential element in reduced pin-count (multi-site) testing. The interfacing needs between the Test Automation World and the Tester Environment are also developed in this paper.

It is becoming evident that testability must be addressed throughout the entire design process. To successfully meet all the design goals of today's and tomorrow's enormously complex devices, swift convergence of function, timing, area and power requirements must be simultaneously accompanied by new test tools that enable rapid, predictable and repeatable DFT closure. Achieving successful DFT closure requires that RTL designers and DFT engineers work in concert on a unified view of the design, using integrated tools and flows. It also requires that DFT tools have zero impact on critically important timing closure flows.

System chips are increasingly designed by embedding reusable cores. A core-based test strategy for such ICs is often attractive and sometimes even mandatory. IEEE P1500 SECT is a standard under development that standardizes a core test language and a core wrapper, in order to facilitate plug-n-play core testing. In this paper, we describe how one standard supports both easy integration and interoperability as well as flexibility and scalability. Possible usage scenarios of the standard for core providers, core users, and EDA tool developers are sketched.

ATPG is about test functionality that leads to test patterns to determine the quality of a chip. Traditionally, this technology has been available at the gate level and this paper describes the need to move higher. High Level is defined as any level in the abstraction chain that is above gates. DRC and DFT technology have already moved to higher levels of abstraction. If necessity is the mother of invention, High Level ATPG is not far behind because the need is there.

Integrated circuits are increasingly designed by embedding pre-designed reusable cores. IEEE P1500 Standard for Embedded Core Test (SECT) is a standard-under-development that aims at improving ease of reuse and facilitating interoperability with respect to the test of such core-based ICs, especially if they contain cores from different sources. This paper briefly describes IEEE P1500, and illustrates through a simplified example its dual compliance concept, its Scalable Hardware Architecture, and its Core Test Language. This paper provides a preliminary, unapproved view on IEEE P1500. The standard is still under development, and this paper only reflects the view of five active participants of the Standardization Committee on its current status.

While technology is changing the face of the world, it itself is changing by leaps and bounds; there is a continuing trend to put more functionality on the same piece of silicon. Without major changes in the CMOS technology, it has been shown that the scaling of devices has significant impact on the effectiveness of Iddq testing. The sensitivity of Iddq testing to individual device parameters is studied. It is explained how Iddq testing becomes increasingly ineffective in the scaled product with respect to most parameters and can be improved with others.

This paper describes a weight generation algorithm that is driven by tests created by a test generator. New concepts with regard to throwing away ineffective weight sets are developed as an integral part of the system. Various parameters that help improve the effectiveness of the weight generation system are discussed.

This paper describes the design of an efficient weighted random pattern system. The performance of the system is measured by the number of weight sets and the number of weighted random patterns required for high fault coverage. Various heuristics that affect the performance of the system are discussed and an experimental evaluation is provided.

The stuck-at fault model has been used over decades as a guide to the test generation process and as an evaluation mechanism for the quality of the test set. As demands on quality have increased, the use of the stuck-at fault model as a predictor of the defect level has been questioned. This paper provides some insight on the issue and shows the limitations of using the stuck-at fault coverage to predict the defect level. The authors demonstrate that as defect level decreases the uncertainty of the estimate grows.>

The standard approach to generating a test set for a logic circuit is to select a set of target fault,s and generate one test for each fault (or at least most of the faults). By far, the most common target fault set is composed of single stuck-at faults. However, many potential manufacturing (non-target) defects are not included in the target fault set, so that their detection is just a fortuitous coincidence. In most cases, many different tests may exist which detect a given single stuck-at fault. However, each of these tests (for the same stuck-at fault) may perform very differently in terms of their non-target defect detection. We investigate this phenomenon empirically using a subset of the ISCXS 85 benchmark circuits, and our results show that extremely wide variations in defective part level are possible over sets of tests which all guarantee 100% single non-redundant stuck-at fault coverage. Our objective in this work is the investigation of non-target defects and their impact on defective part level. Here, our thrust is not to develop new test gene rut i o n methods .

The nature of many problems related to testability requires detailed information about their underlying test parameters. These parameters are commonly referred to as controllability and observability. This research concerns exact measures of detectability, controllability, and observability to measure the relative importance of the latter two on the likelihood of the former. New functional methods for fault analysis are utilized which allow computations not previously possible; the empirical results presented here are an example of such an application.>

An algorithm for bounding the random pattern testability of individual faults in a circuit is proposed. Auxiliary gates for bounding the testability are constructed, converting the problem into one of determining the signal probability at the output of the auxiliary gate. The results presented are in terms of lower bounds of the testabilities of faults. The bounds generated by the algorithm can be used by designers to identify pseudorandom pattern resistant faults, to enable them to modify the circuit structure to make the faults easy to detect, and, hence, to increase the fault coverage.>