Testing and simulation are critical to accurate onchip electrostatic discharge (ESD) protection designs, particularly for complex ICs in advanced technologies. This paper discusses two important considerations in practical on-chip ESD protection designs. First, accurate ESD design simulation relies on ESD testing for calibration where the input ESD stimulus plays a key role in precisely correlating ESD simulation with ESD testing, e.g., using human body model (HBM) ESD zapping and transmission-line pulse (TLP) measurement. Second, very-fast TLP (VFTLP) testing is widely used for charged device model (CDM) ESD characterization, which is questionable because transitional pad-based CDM ESD protection method may be fundamentally wrong. Understanding these two ESD testing factors are critical to ESD design optimization and prediction, as well as ESD protection validation.

Electrostatic discharge (ESD) can cause malfunction or failure of integrated circuits (ICs) . On-chip ESD protection design is a major IC design-for-reliability (DfR) challenge, particularly for complex chips made in advanced technology nodes. Traditional trial-and-error approaches become unacceptable to practical ESD protection designs for advanced ICs. Full-chip ESD protection circuit design optimization, prediction, and verification become essential to advanced chip designs, which highly depends on CAD algorithm and simulation that has been a constant research topic for decades. This paper reviews recent advances in CAD-enabled on-chip ESD protection circuit simulation design technologies and ESD-IC co-design methodologies. Key challenges of ESD CAD design practices are outlined. Practical ESD protection simulation design examples are discussed.

In this paper, we present an in-depth study of light emitting diode (LED) based indoor visible light communication positioning system using a smart phone camera with rolling shutter effect, aiming for smart and connected hospital applications. The LED transmits periodical signals with different frequencies as its optical tags. The camera exploits the rolling shutter effect to detect the fundamental frequency of optical signals. The roles of camera parameters determining the rolling effect are studied and a technique to measure the camera readout time per column is presented. Factors limiting the detectable optical frequency range is explained based on the discussion of rolling shutter mechanism. The Fourier spectrum based frequency resolution, which determines the tracking capacity, is analyzed.

Full-chip electrostatic discharge (ESD) protection circuit design verification is needed for complex ICs at advanced technology nodes despite being largely impractical due to the limitation of ESD device models and CAD tools. This paper reports a new circuit-level ESD protection design simulation and dynamic checking method using SPICE and ESD device behavior models which allows comprehensive, quantitative, and dynamic verification of ESD protection circuit designs at chip level-based entirely on ESD discharging functions. The new ESD protection circuit simulation method is validated using ICs designed and fabricated in a 28 nm CMOS. This ESD-function-based ESD circuit simulation method is technology independent, which can handle various ICs including complex multiple power domain circuits and ICs using nontraditional ESD protection structures.

This paper reports a new scalable behavioral modeling technique for silicon controlled rectifier (SCR) based electrostatic discharge (ESD) protection structures using Verilog-A language. Accurate models were developed for various low-triggering voltage SCR ESD (LVSCR) protection structures implemented in a foundry 180nm RF process, which were validated by circuit simulation and ESD measurement.

This paper presents a 65nm multi-mode complex band-pass filter (C-BPF) used in low-IF GNSS receivers. It supports the bandwidth of 4MHz, 10MHz and 18MHz, and can be centered at 4.2MHz, 6.1MHz, 12.3MHz and 28MHz. The OTAs served in the filter are realized in arrays which makes the power consumption scalable among different operation modes. In addition, assistant transconductors (assistant-gm) are adopted to compensate the outputs of each OTA stage, which in turn saves at maximum 9mA DC current for the whole filter. In order to achieve higher than 30dB image rejection ratio (IRR), another group of assistant-gms are introduced to the input stage for I/Q mismatch calibration, which is able to regulate a maximum ±3dB amplitude imbalance and ±5° phase imbalance. The filter consumes less than 10mA in the 28MHz-IF, 18MHz-bandwidth mode, and achieves >31dB IRR with the maximum I/Q amplitude and phase mismatch.

We report design and analysis of full-chip ESD protection solution for high-voltage (HV) mixed-signal ICs in a BCD30V technology by mixed-mode ESD simulation involving integrated process, device, circuit and layout co-design. The full-chip HV ESD protection scheme includes both I/O and power clamp ESD protection. Mixed-mode ESD simulation technique enables pre-Si ESD design optimization and prediction. ESD measurements confirm full-chip HV ESD protection of >4.5KV for the whole chip. This design technique can be applied to practical full-chip HV ESD protection circuit design for mixed-signal ICs in various HV BCD technologies.

A half-rate clock and data recovery (CDR) circuit for 60GHz communication with 20Gbps QPSK modulation in 65nm CMOS is presented. A hybrid DC-offset cancellation loop (DCOC) is proposed to calibrate the input offset. A duty cycle distortion (DCD) cleaning up circuit is adopted to minimize the negative impact on the half rate sampling in the CML-CMOS conversion, and a quadrature clock calibration (QCC) is utilized to correct the input clock I/Q phase mismatch. The CDR is based on phase interpolator (PI) and uses the quadrature clocks from the divider of the main PLL. The whole CDR consumes less than 16mW with 1V power supply and achieves less than 1mV DC-offset, 0.2% DCD and less than 1° residual I/Q phase mismatch after calibration.

For decades, advances in integrated circuits (IC) have been driven by continuous scaling down of planar IC technologies. As IC scaling rapidly approaches to technical brick wall, 3D IC heterogeneous integration emerges as a viable solution for future integrated electronics. Future complex system-on-a-chip (SoC) requires high-performance active devices, and novel passive and supporting devices. This paper reviews recent advances in develop 3D magnetic-enhanced inductors and 3D on-chip electrostatic discharging (ESD) structures to achieve heterogeneous 3D ICs with high performance and reliability simultaneously.

A low-power full 3.1-10.6 GHz UWB transmitter using very simple 4-delay-cell 5th-derivative Gaussian pulse generation for carrier-free IR-UWB system is designed and fabricated in 0.13 mum CMOS. The fully integrated IR-UWB transmitter features on-chip compensated active balun and simple BPSK modulation. Measurement shows the lowest reported power of 33 pJ/pulse at 100 MHz PRF, short 5th-derivative Gaussian pulse width of 750 ps and Vppof 84 mV. This FCC-compliant IR-UWB transmitter allows up to 1.3 Gbps throughput for low-cost low-power hi-QoS wireless multimedia and video streaming.

A fully integrated, ultra low-power, varying pulse width second-order derivative Gaussian pulse generator designed and fabricated in a commercial 0.18μm CMOS technology is reported for 3-10GHz ultra wideband (UWB) transceivers. The second-order derivative Gaussian pulse generator circuit consists of three cascaded stages for generating square wave, Gaussian impulse, and second-order derivation sequentially. This CMOS second-order derivative Gaussian pulse generator can generate UWB pulses with adjustable pulse width ranging from 220 picoseconds to a few nanoseconds. Measured circuit performance achieves a very short pulse width of <1ns, an amplitude of 70mV and an ultra low power consumption of 2mW at 100MHz pulse repeating frequency. The pulse generator fully complies with FCC power mask.

This paper presents a curvature-compensated bandgap reference (BGR) circuit implemented in 0.35 /spl mu/m CMOS technology. The circuit delivers an output voltage of 1.09 V and achieves a temperature coefficient of 3.1 ppm//spl deg/C over [-20/spl deg/C, 100/spl deg/C] after trimming, a power supply rejection ratio of -80 dB at 1 KHz and an output noise level of 1.43 /spl mu/V/sqrt(Hz) at 1 KHz. The BGR circuit consumes a current of 37 /spl mu/A and the power supply ranges from 1.5 V to 3.3 V.

On-chip ESD (electrostatic discharging) protection is a challenging IC design problem. New CAD tools are essential to ESD protection design prediction and verification at the full chip level. This paper reports a new CAD tool, entitled ESDZapper, to simulate the complex ESD protection zapping test, procedures and to find the critical discharging path under a specific ESD stress. ESDZapper is developed based on a novel concept of ESD-critical parameters. Capability of the new tool is demonstrated using a practical design example in a 0.35μm BiCMOS technology.

On-chip electrostatic discharge (ESD) protection design is a challenging IC design problem. New computer-aided design (CAD) tools are essential to ESD protection design prediction and verification at full chip level. This paper reports a novel smart parametric-checking mechanism and a new intelligent CAD tool, entitled ESD inspector, developed for full-chip ESD-protection circuitry-design verification. Capability of the new tool is demonstrated using a practical design example in a 0.35-/spl mu/m BiCMOS technology.

New challenge in ESD protection design for RF ICs is to address the complex interactions between the ESD protection network and the core circuit being protected in both directions. This paper reviews recent developments in RF ESD protection design, including switching and mis-triggering of ESD protection networks; ESD-induced parasitic capacitive, resistive, noise coupling and self-generated noise effects; RF ESD evaluation techniques; and low-parasitic compact RF ESD protection solutions.

The challenges for developing an on-chip electrostatic discharge (ESD) protection circuit layout extractor originate from unconventional layout patterns of ESD protection devices, parasitic ESD device extraction, and device count reduction. This paper reports a new technology independent layout extractor called the ESDExtractor, which is capable of extracting arbitrary ESD protection devices and answers the demands for full-chip ESD protection design verification. The general methodology to extract both intentional and parasitic ESD protection devices, the specific algorithms, and implementation methods to enhance ESDExtractor's efficiency are presented. Finally, the capability of the new computer-aided design tool is demonstrated using application examples.

The challenges for developing an ESD (Electro-static Discharge) layout extractor originate from unconventional layout patterns of ESD protection devices, parasitic ESD device extraction and device count reduction. This paper reports a new technology-independent layout extractor, ESDExtractor, which is capable of extracting all types of ESD devices and answers the demands for ESD design verification. General methodology to extract both intentional and parasitic ESD devices, specific algorithms and implementation methods for efficiencyenhancement are presented, followed by a design example.