In this paper a new VCO-based MASH delta-sigma ADC structure is presented. The proposed architecture does not require any OTA-based analog integrators or integrating capacitors. Second-order noise shaping is achieved by using a VCO as an integrator in the feedback loop of the first stage and an open loop VCO quantizer in the second stage. Simple digital circuitry extracts the phase quantization error of the first stage as a pulse signal that is applied to the second stage. Based on the architecture, the input of the first VCO is a very small signal and the input of the second VCO is a two-level PWM signal. Therefore, the VCO non-linearity does not limit the overall ADC performance, mitigating the need for power hungry linearization methods. Behavioral-model simulations show a 70 dB SNDR improvement from a standalone open loop VCO-based ADC in the presence of nonlinearity.

Recent analog designers do think about measurement at design time. Analog design-for-measurement is a real success, not based on test research but based on designers' incorporation of calibration methods to ensure that their circuits work within specifications. In the meantime, mixed-signal test research has not kept pace with new design architectures, and some analog designers have outpaced mixed-signal test/design-for-test researchers. This session will elucidate the key factors for this success and the differences between design and test. And the session will discusses a designers' and test researchers' roles on analog design-for-test from each viewpoint, and some challenges on collaborating designers and test researchers.

Delay insensitive asynchronous circuitry provides significant advantages with respect to substrate noise due to localized switching. The differences between the substrate noise from NULL convention logic (NCL) and traditional clocked Boolean logic (CBL) are described and analyzed based on measured results. A test chip fabricated in the TSMC 0.25 μm process shows that a pseudo-random number generator implemented with NCL generates 23 dB less substrate noise compared to the equivalent synchronous design. In a larger scale digital circuit, the substrate noise improvement offered by an asynchronous 8051 processor over its synchronous counterpart was nearly 10 dB. The effect of this substrate noise on an analog circuit was explored with a delta-sigma modulator (DSM) example. The signal-to-noise ratio performance of a second order DSM was not affected by the substrate noise from the NCL 8051 processor while it experiences up to 15 dB degradation when the CBL 8051 processor is clocked near integer multiples of the DSM sampling frequency.

This paper presents a new zero-optimization scheme for noise-coupled ΔΣ analog-to-digital converters (ADCs). The proposed technique enhances the signal-to-quantization-noise-ratio (SQNR) by optimizing noise-transfer-function (NTF) zero locations to get maximum in-band noise shaping. The amount of SQNR improvement using the new scheme depends on the order of the modulator. Therefore, zero optimization will be used in a first-order and a second-order modified noise-coupled ΔΣ ADCs. The proposed technique enhances the SQNR of the first-order and second-order noise-coupled ΔΣ modulators by 4.5dB and 8.5 dB, respectively.

A novel low power hybrid (Active-Passive) loop filter using the single amplifier biquad (SAB) filter is presented. This new hybrid loop filter saves power consumption by reducing the number of active elements in the continuous-time sigma-delta modulator. Also, the core biquad filter allows the loop filter of a high-order modulator to be implemented by cascading low-order biquad sections, considerably easing the design and implementation of the high-order continuous-time sigma-delta modulator. The proposed loop filter is a general type of hybrid filter which could be used for the both high and low oversampling ratios (OSRs). Experiment on a 5th-order low pass continuous-time sigma-delta modulator with a bandwidth of 30 MHz is conducted successfully and the results are presented.

A new green function-based method for extracting parasitics in inhomogeneous substrates is presented. This approach overcomes the limitation of prior green function-based methods and allows extraction of substrate parasitics in the presence of sinkers, trenches, and wells. A careful use of volume and boundary-element meshing, as well as discrete transforms, yields a technique that is computationally efficient. The accuracy of the method is comparable to that of 3-D semiconductor device simulators with significantly smaller computational costs.

Key issues in wireless receivers for wireless sensor networks are discussed and existing implementations are compared. On the system level, a new method to determine power allocation is developed to ensure system requirements are met while minimizing power consumption. On the circuit level, several common designs are reevaluated in the context of low power design and the best choices for low power CMOS receiver design are given. A noise analysis shows that for extremely low power operation, the common gate LNA provides better noise performance over the commonly used common source design. Existing filters are compared and a figure of merit is used to determine the best architecture for low power design. Circuit simulations are used to show that a higher power limiting amplifier can reduce the overall receiver power for a given set of noise and gain specifications.

A new super-regenerative transceiver for use in low power binary frequency shift keying (BFSK) digital communication systems is presented. The classic on/off keying (OOK) design is reviewed and motivation to extend the design to BFSK is given. The system is shown to preserve the low power qualities of the classic super-regenerative transceiver while obtaining the increased speed and reliability of BFSK modulation. Operation of the new system is explained at the system level and insight into the circuit design is also given. Simulations show the transceiver allows transmission rates on the order of 250kbps with a link power of less than 1.4mW.

This paper presents an error control method for application of the discrete cosine transform (DCT) to extraction of substrate parasitics in integrated circuits. In addition to the truncation error with approximating an infinite series with a finite number of terms, there are also errors in approximating the truncated series by the DCT. It is shown that this error is important for accurate parasitic extraction and isolation calculation and can be controlled by applying an interpolation method. The interpolation method also makes it possible to use a smaller DCT size without loss of accuracy.

This paper presents a new Green function-based approach for substrate parasitic extraction in substrates with inhomogeneous layers. This new formulation allows analysis of noise coupling with sinkers, trenches and wells, - a limitation in prior Green function-based extractors. Numerical examples for sinkers and trenches are provided and compared with the results from threedimensional semiconductor device simulations. It is shown that the proposed method is accurate and computationally efficient.

This paper presents an analysis of the numerical stability for the formulation of the Green's function method of Niknejad et al. (1998) for modeling and analysis of substrate coupling in integrated circuits. It is shown that the formulation has numerical overflow problems. A new stable formulation is presented.

A new method is presented to compress switching information in large synchronous digital circuits. This is combined with an efficient generation of digital cell library noise signatures and results in an accurate estimation of the switching noise in digital circuits. It provides a practical approach to generating the digital switching noise for simulating substrate coupling noise in mixed-signal ICs. Nearly two orders of magnitude reduction in the memory and simulation time are achieved using this approach without significant loss of accuracy.

This paper presents an automated methodology for calibrating the doping profile and accurately predicting substrate parasitics with boundary element solvers. The technique requires fabrication of only a few test structures and results in an accurate three-layered approximation of a heavily doped epitaxial silicon substrate. Using this approximation, the extracted substrate resistances are accurate to within 10% of measurements. The calibrated parasitic extractor results in good agreement between simulations and measurements for substrate noise coupling in fabricated test circuits.

A scalable macromodel for substrate noise coupling in heavily doped substrates has been developed. This model is simple since it requires only four parameters which can readily be extracted from a small number of device simulations or measurements. Once these parameters have been determined the model can be used for any spacing between the injection and sensing contacts and for different contact geometries. The scalability of the model with separation and width provides insight into substrate coupling and optimization issues prior to and during the layout phase. The model is validated for a 2 /spl mu/m and a 0.5 /spl mu/m CMOS process where it is shown that the simple model predicts the noise coupling accurately. Measurements from a chip fabricated in a 0.5 /spl mu/m CMOS process show good agreement with the model.

Abstiact-An efficientCA1OStramistor stack generation procedure for analog circuits is d=eribed.The matchmg mqutiments are used as the primary comtraint on the artatog layou~however,parasitic mpacitances and area eomideratiorrsare also included.A designer chosenarbitrary circuit partition from the srhematic a be used to generate the corresponding layout as an optimum stack of transistors with completeintra-module connectivity.The port structures are consideredm part of the modulearea and parasitic optbrdntion procedure.The results are demonstrated through an exampleand a completeebip layout of a high-resolutiondelta-sigmaartafo~ to-digitalconverter.

Article Free Access Share on A low voltage CMOS current source Authors: Detlev Schmitt School of EECS, Washington State University, Pullman, WA School of EECS, Washington State University, Pullman, WAView Profile , Terri S. Fiez School of EECS, Washington State University, Pullman, WA School of EECS, Washington State University, Pullman, WAView Profile Authors Info & Claims ISLPED '97: Proceedings of the 1997 international symposium on Low power electronics and designAugust 1997 Pages 110–113https://doi.org/10.1145/263272.263301Published:01 August 1997Publication History 7citation1,076DownloadsMetricsTotal Citations7Total Downloads1,076Last 12 Months24Last 6 weeks10 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF

A new dynamic element matching (DEM) algorithm, referred to as data weighted averaging (DWA), is presented for improving DAC linearity in multi-bit delta-sigma (/spl Delta//spl Sigma/) data converters. It out-performs all previously described algorithms. By cycling through the elements of the DAC at a rate dependent on the input to the DAC, the elements of the DAC are exercised at the maximum rate possible. With this algorithm, the distortion spectra are shaped by first-order noise shaping which results in 9 dB/octave improvement in the converter dynamic range when DAC errors dominate the performance. Simulating a third-order 3-bit modulator with an oversampling ratio of 128 and 1% DAC element matching, 110 dB signal-to-noise ratio (18 bits) is achieved by employing DWA DEM.

This paper presents and compares two new digitally programmable structures for the control of DC to DC switching power supplies. The first structure is a switched capacitor, proportional plus integral (PI) based pulse width modulated (PWM) controller with automatic circuit offset and mismatch absorption. The second structure uses a proportional plus integral plus derivative (PID) structure as input to a first order delta-sigma (/spl Delta//spl Sigma/) modulator to eliminate circuit and matching requirements found in existing control structures. It makes use of the low-pass filtering effects of the power supply to filter out the high frequency quantization noise associated with the /spl Delta//spl Sigma/ modulator. Simulation and discrete component lab tests indicate 2% to 3% load regulation with up to 100 Watts of output power.

A simple model for the MOS transistor small-signal drain-source resistance, /spl tau//sub ds/, is presented that accurately predicts analog circuit performance. It is ideal for first-order analog circuit hand calculations. The drain current, I/sub ds/, has exactly the same form as the conventional square-law model. The channel length modulation parameter, X, is modified based on two dimensional analysis to produce a simple model that matches measured devices to within 5% even for short devices.>

This paper presents an asynchronous version of the Add-Compare-Select (ACS) processor. It is shown that in a statistical sense the asynchronous version of the ACS processor is faster than the synchronized version. Thus, it provides an alternative solution to overcome the speed bottleneck of the ACS processor for the Viterbi processor. An 8-bit asynchronous ACS processor requires 1.2 mm/spl times/1.2 mm in a 2/spl mu/ CMOS technology.>

The design of an A/D converter for the next generation of processes requiring lower supply voltages is explored through the design and implementation of a 12 bit converter in a 1.2 /spl mu/m digital CMOS process using a 2 V analog power supply. The resulting chip is 22.4 mm/sup 2/ and is presently being tested. It is expected to achieve a 1 MHz sampling rate with an analog power dissipation of 60 mW.>