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Charles W. Cha

dblp:96/3241 · DBLP profile ↗
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3ranked-venue papers
3as first author
0since 2021 · last 1979
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3 · 3 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
3 papers
Electronic design automation · 89% Distributed systems · 11%

Topics — the 7 heaviest of 7, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation
hardware verification and test		 0.031979
Multiple fault diagnosis in combinational networks · DAC 1979
9-V Algorithm for Test Pattern Generation of Combinational Digital Circuits · IEEE Trans. Computers 1978
A testing strategy for PLAs · DAC 1978
Electronic design automation › hardware verification and test
test generation		 0.021978
9-V Algorithm for Test Pattern Generation of Combinational Digital Circuits · IEEE Trans. Computers 1978
A testing strategy for PLAs · DAC 1978
Electronic design automation › hardware verification and test
fault diagnosis		 0.011979
Multiple fault diagnosis in combinational networks · DAC 1979
Distributed systems
fault tolerance		 0.011979
Multiple fault diagnosis in combinational networks · DAC 1979
Electronic design automation › hardware verification and test › fault diagnosis
multiple fault diagnosis		 0.011979
Multiple fault diagnosis in combinational networks · DAC 1979
Electronic design automation › hardware verification and test › test generation
path sensitization		 0.011978
9-V Algorithm for Test Pattern Generation of Combinational Digital Circuits · IEEE Trans. Computers 1978
Electronic design automation › hardware verification and test › VLSI testing
programmable logic array testing		 0.011978
A testing strategy for PLAs · DAC 1978

Methods — techniques the papers use, named apart from their topics

nine-valued logic calculus · 0.0
YearPublicationVenuePosition
1979 Multiple fault diagnosis in combinational networks
Charles W. Cha
 DAC1
1978 A testing strategy for PLAs
Charles W. Cha
 DAC1
1978 9-V Algorithm for Test Pattern Generation of Combinational Digital Circuits
abstract
An algorithm for generating test patterns for combinational circuits has been developed and programmed. The algorithm is definitive and finds a test for all faults including those that require multiple paths to be sensitized, by sensitizing a single path at a time and trying at most each single path. This is achieved by using a new calculus based on nine values (0,1,D,D̄,0/D,0/D̄, 1/D,1/D̄,U). One path is deliberately sensitized while the alternative paths are assigned values which permit the option of desensitizing or sensitizing them as the sensitized path is developed. Experimental results are presented for a variety of cases.
Charles W. Cha, Wilm E. Donath, Füsun Özgüner
 IEEE Trans. Computers1