The Interaction Design and Children (IDC) Community has a long history of innovating methods and techniques for the design and evaluation of technologies for children. Many innovations have been reported in the academic literature but the uptake of methods by industry has been slow and the community has hitherto failed to seriously consider how best to develop, present and promote their methods beyond academia. The aim of the workshop is to weave together IDC researchers and IDC key personnel coming from the industry, with genuine interest in industry-academia collaboration, into a community interested in building a coherent, high-impact collaboration channel. The goal of the workshop is to encourage a critical discussion and debate about how IDC methods can be further adopted, modified or even extended by the IDC related industry. This workshop is expected to reinforce IDC industry-academia collaboration with an ultimate goal to increase understanding and develop a community of interest that is going to co-develop ideas and novel design approaches that can bring IDC methods closer to the industrial practice

Model Based Design tools based around Simulink from The MathWorks are a popular technology for the creation of streaming DSP designs for FPGAs, since they offer the promise of rapid design exploration through immediate quantitative feedback of algorithm performance. Current tools typically use a library of components that reflect an explicit representation of the underlying FPGA device features. This is undesirable since the designer is forced to mix implementation and architecture, and leads to long design cycles and non-portable results. This paper shows that introducing techniques of high level synthesis allows a more elegant design at a higher level of abstraction. This results in fewer components needed for a design which translates into a faster design cycle, more portable designs and fewer defects. Pushbutton clock frequencies of up to 500 MHz are achieved without detailed knowledge of FPGA architectures. Although the capabilities described are embodied in the DSP Builder tool from Altera, this paper describes the technology involved rather than the details of the tools. Four major technologies are described: a latency-insensitive system representation, the module level internal representation with associated transformations, hardware retiming, and lastly a FIR filter design tool layered on top.

The traditional use of a design rule checker (DRC) ensures that the layout of an integrated circuit conforms to a set of tolerances known as design rules. Integrated circuit manufacturing yields are enhanced if these tolerances are not violated. In contrast to tolerance checking, yield analysis concerns itself with “yield sensitive elements” such as number of devices, total areas and total length of lines. The cumulative distributions of the elements can be used in yield analysis modeling. In addition, the value distribution of each element can be used to model the processing effort required for yielding a design. A software system known as YIELD is essential for extracting the required statistical data from the graphical data base.