Radiation-Induced single event upsets (SEUs) significantly damage the reliability of Deep Convolution Neural Networks (DCNNs) in harsh environments, i.e., deep space. Stochastic computing (SC) has exhibited the outstanding tolerance against SEUs via diluting a binary weight in a longer stochastic stream. However, the exponential expanding of stochastic streams and multi-layer neural networks together incur an unaffordable hardware consumption in their fully hardened SC-DCNN circuits. In this paper, SCArmor, a genetic evolution-based hardening framework, is proposed to select the critical bits and layers fast for the reliable and lightweight anti-radiation designs. First, a layer-wise error propagation model (LEPM) is built to evaluate the layer-sensitivity that indicates how many of a faulty-layer errors propagated to the downstream, serving as the reliability weights across the layers in SC-DCNNs. Second, the bit-sensitivity is modeled with sensitivity-driven fault injection (SDFI) to highlight those critical bits in both stochastic and unary numbers, which are further accumulated within a layer, i.e., convolution, activation, pooling, and full connection, to estimate the fault-tolerant abilities of the individual layers. Finally, by jointly using above two sensitivities as the fast emulation of inference accuracy, a re-training-free genetic algorithm is embedded into the hardening framework to locate the primary layers and SC-bits that should be hardened under the constraints of both inference accuracy and circuit cost. On the popular SC-DCNNs, the results show that, compared with the SOTA hardening methods, SCArmor reduces the area, power, and latency by 22.21%, 29.69%, and 43.15% respectively, only using 42.46% cost of full-hardening approaches. Regarding reliability, the accuracy of SCArmor achieves up to 98.63% of that of the radiation-free inference, outperforming the SOTAs by 3.13%.

Traffic congestion has become a serious problem in large hospital located in the areas with the high-density population. To mitigate the serious traffic congestion situation so that patients can timely obtain diagnosis and treatment, by accessing real-time monitoring traffic data from a provincial Maternal and Child Health Care Hospital, we propose and simulate three proposed traffic management strategies based on hospital traffic characteristics and the estimated traffic volume through a model developed based on the queueing theory. The results show that the three proposed strategies can relieve the traffic congestion faced by the large hospital.

Hospital emergency management is an important issue because of the characteristics of hospital constructions, patients, and environment. In this study, a BIM-based integrated multiple level emergency management is proposed in the large hospital context. The framework includes the seamless integration of BIM operation and management models, the evaluation of risk level and the analysis of corresponding emergency response plans. The framework should provide a significant guidance for smart hospital emergent management both in academic and practice.

Pedestrian detection is an important example of object detection and has attracted much attention. Many works have shown that good image features provide high detection accuracy, and a few works have investigated enhancing low-level features (e.g., gradient and color features) using a filtered layer (i.e., convolutional layer) to obtain enhanced features or filtered channel features. To investigate whether these features are saturated, this paper adopts the concept of filtered channel features and strengthens them by adding more convolutional layers. Acting as convolution kernels, multilayer filters are applied to low-level features to obtain the extended filtered channel features, providing a powerful feature extractor with multilayer transformation for pedestrian detection. The proposed extended filtered channel framework (ExtFCF) achieves competitive performance on widely used benchmark datasets (Caltech, INRIA, and KITTI datasets), using only histogram of oriented gradient (HOG) and CIE-LUV [a color space composing of luminance (L) and two chrominance (UV) components by International Commission on Illumination] color features (HOG+LUV) as low-level features. One representative ExtFCF implementation achieves the best result compared with the current best traditional pedestrian detection methods on the Caltech dataset.

With technology scaling, integrated circuits behave more unpredictably due to process variation, environmental changes and aging effects. Various variation-aware and adaptive design methodologies have been proposed to tackle this problem. Clearly, more effective solutions can be obtained if we are able to collect real-time information such as the actual propagation delay of critical paths when the circuit is running in normal function mode. Motivated by the above, in this paper, we propose a novel concurrent online delay measurement architecture for critical paths, namely CODA, to facilitate this task. Experimental results demonstrate high accuracy and practicality of the proposed technique.

When testing delay faults on critical paths, conventional structural test patterns may be applied in functionally-unreachable states, leading to over-testing or under-testing of the circuits. In this paper, we propose novel layout-aware pseudo-functional testing techniques to tackle the above problem. Firstly, by taking the circuit layout information into account, functional constraints related to delay faults on critical paths are extracted. Then, we generate functionally-reachable test cubes for every true critical path in the circuit. Finally, we fill the don't-care bits in the test cubes to maximize power supply noises on critical paths under the consideration of functional constraints. The effectiveness of the proposed methodology is verified with large ISCAS'89 benchmark circuits.

Power distribution network (PDN) designs for today's high performance integrated circuits (ICs) typically occupy a significant share of metal resources in the circuit, and hence defects may be introduced on PDNs during the manufacturing process. Since we cannot afford to over-design the PDNs to tolerate all possible defects, it is necessary to conduct manufacturing test for them. In this paper, we propose novel methodologies to identify those potentially harmful open defects in PDNs and we show how to select a set of patterns that initially target transition faults to achieve high fault coverage for the PDN defects. Experimental results on benchmark circuits demonstrate the effectiveness of the proposed technique.

The test time for core-external interconnect shorts and opens is typically much less than that for core-internal logic. Therefore, prior work on test-infrastructure design for core-based system-on-a-chip (SOC) has mainly focused on minimizing the test time for core-internal logic. However, as feature sizes shrink for newer process technologies, the test time for signal integrity (SI) faults on interconnects cannot be neglected. The test time for SI faults can be comparable to, or even larger than, the test time for the embedded cores. We investigate the impact of interconnect SI tests on SOC test-architecture design and optimization. A compaction method for SI faults and algorithms for test-architecture optimization are also presented. Experimental results for the ITC'02 benchmarks show that the proposed approach can significantly reduce the overall testing time for core-internal logic and core-external interconnects.

Large test data volume and high test power are two of the major concerns for the industry when testing large integrated circuits. With given test cubes in scan-based testing, the ldquodonpsilat-carerdquo bits can be exploited for test data compression and/or test power reduction. Prior work either targets only one of these two issues or considers to reduce test data volume and scan shift power together. In this paper, we propose a novel capture power-aware test compression scheme that is able to keep scan capture power under a safe limit with little loss in test compression ratio. Experimental results on benchmark circuits demonstrate the efficacy of the proposed approach.

The test time for core-external interconnect shorts/opens is typically much less than that for core-internal logic. Therefore, prior work on test infrastructure design for core-based system-on-a-chip (SOC) has mainly focused on minimizing the test time for core-internal logic. However, as feature sizes shrink for newer process technologies, the test time for interconnect signal integrity (SI) faults cannot be neglected. We investigate the impact of interconnect SI tests on SOC test architecture design and optimization. We present a compaction method for SI faults and algorithms for test architecture optimization. Experimental results for the ITC'02 benchmarks show that the proposed approach can significantly reduce the overall testing time for core-internal logic and core-external interconnects.

As feature sizes continue to shrink for newer process technologies, signal integrity (SI) is emerging as a major concern for core-based system-on-a-chip (SoC) integrated circuits. To effectively test SI faults on core-external interconnects, core test wrappers need to be able to generate appropriate transitions at a wrapper output cell (WOC) on the driving side and detect the signal integrity loss at a wrapper input cell on the receiving side. In current wrapper designs, the WOCs for a victim interconnect and its aggressors make transitions at the same time with a common test clock signal in test mode, which is different from the functional mode. This is not adequate for SI test because the time elapsed between the transition of the victim and the transitions of its aggressors significantly affects the behavior of SI-related errors. To address this problem, we propose new IEEE Std. 1500-compliant wrapper designs that are able to apply SI test at functional mode or make transitions with various pre-defined skews between a victim line and its aggressors. We also introduce a novel overshoot detector inside the proposed wrapper. Experimental results show that the proposed wrapper designs are more effective for detecting SI-related errors when compared to existing techniques, with a moderate amount of DFT overhead.

This paper presents a new approach to implement a full range window comparator (FRWC) with self-testing capability. Detailed analysis of the proposed comparator circuit has shown that the overall design not only can achieve high fault coverage in the FRWC but also can detect or tolerate single fault in the self testing circuitry used.