This paper presents a fractional-N all digital phase locked loop (ADPLL) based on a new quad-core class-F3oscillator, which reduces the out-of-band phase noise of ADPLL. The LC tank of the proposed oscillator incorporates both parallel and series resonant cavities compactly. It increases an additional impedance peak around the third-harmonic of the fundamental oscillation voltage, thus enforcing a pseudo-square voltage waveform around the LC tank. Consequently, the effective impulse sensitivity function (ISF) decreases, thereby reducing the phase noise. Furthermore, the proposed topology demonstrates low phase noise penalty during multi-core resonance. The ADPLL is implemented in a 40nm CMOS process. The simulated phase noise of the quad-core class-F3oscillator at 1MHz offset varies from -124.5 to -126.1dBc/Hz depending on the output frequency, which ranges from 10.29 to 12.75GHz. The oscillator consumes 24.36mW from the supply and exhibits a figure-of-merit (FoM) of 192.5dBc/Hz. Ultimately, the ADPLL utilizing the proposed oscillator exhibits an excellent RMS jitter of 49.7fs and achieves a FoM of -250.5dB.

This paper describes a 4T4R ultra-wideband transceiver (UWB TRX) with compact baseband shifter and digital phase interpolar (DPI) for beamforming to alleviate the contradiction between power consumption and performance. A complementary stacked multi-supply switched-capacitor power amplifier (SCPA) is introduced for efficiency. It allows PA work in both high output and low output mode, which makes the proposed transceiver could work as traditional short-ranging communication and ranging UWB TRX or as a 4 elements beamforming TRX for better system efficiency and sensitivity. A bounding wire based in-chip inductor less matching network is adopted for wide band and farther reducing the chip area. Implemented in 22nm CMOS technology, the proposed TRX works from 3GHz to 10GHz, achieve 3.7–4.2 dB NF and 57.1%@11.8dBm / 48%@-0.23dBm drain efficiency, occupies 8.72mW for RX and 31.9mW / 9.6mW for TX per channel.

Backscatter transceivers are often used in ultra-low-power Internet of Things (IoT) applications. However traditional backscatter transceiver (TRX) cannot actively control the transmitted power, which greatly limits the communication distance. This paper introduces a novel backscatter TRX operating in the ultra-high frequency (UHF) band, with a low power consumption of only 136μW and an impressive communication range surpassing 800 meters. Unlike the backscatter, the received continuous wave (CW) is not reflected via impedance modulating at the antenna but is directed into the TRX to be modulated and amplified. This technique significantly extends the communication range at a low power consumption. A coupler serves to prevent the direct entry of transmitted signals into the receiving path, ensuring the received CW remains unaffected to be modulated. Implemented in TSMC 40nm CMOS, the proposed TRX core occupies 0.7 mm2and works under a 0.7V supply voltage with the -54.6dBm input power and -20dBm output power.

During the last years, the growing application complexity, design, and mask costs have compelled embedded system designers to increasingly consider partially reconfigurable application-specific instruction set processors (rASIPs) which combine a programmable base processor with a reconfigurable fabric. Although such processors promise to deliver excellent balance between performance and flexibility, their design remains a challenging task. The key to the successful design of a rASIP is combined architecture exploration of all the three major components: the programmable core, the reconfigurable fabric, and the interfaces between these two. This work presents a design flow that supports fast architecture exploration for rASIPs. The design flow is centered around a unified description of an entire rASIP in an architecture description language (ADL). This ADL description facilitates consistent modeling and exploration of all three components of a rASIP through automatic generation of the software tools (compiler tool chain and instruction set simulator) and the RTL hardware model. The generated software tools and the RTL model can be used either for final implementation of the rASIP or can serve as a preoptimized starting point for implementation that can be hand optimized afterward. The design flow is further enhanced by a number of automatic application analysis tools, including a fine-grained application profiler, an instruction set extension (ISE) generator, and a data path mapper for coarse grained reconfigurable architectures (CGRAs). We present some case studies on embedded benchmarks to show how the design space exploration process helps to efficiently design an application domain specific rASIP.