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Sundar Iyengar

dblp:96/4200 · DBLP profile ↗
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3ranked-venue papers
0as first author
1since 2021 · last 2026
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3 · 1 since 2021Software engineering, systems software and programming languages · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 100%

Topics — the 2 heaviest of 2, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › hardware description language
graphical design language
0.011988
A Graphical Hardware Design Language · DAC 1988
Electronic design automation
hardware description language
0.011988
A Graphical Hardware Design Language · DAC 1988
YearPublicationVenuePosition
2026 SPEC CPU: The Next Generotion
abstract
The march toward developing relevant and robust CPU benchmarks continues with the introduction of SPEC CPU 2026, the next generation suite for measuring processor performance. This paper details the methodology behind its creation, showcasing a process centered on community collaboration and principled development. The suite is built upon a foundation of modern, open-source applications, selected and hardened through a process that emphasizes workload diversity, portability, and software longevity. A key contribution is Rolling-Round-Robin Rate, a novel and standardized approach to running heterogeneous, multiprogrammed workloads that addresses a long-standing gap in benchmarking practice. Additionally, the suite features an expanded set of multithreaded benchmarks and introduces workloads with distinct microarchitectural profiles, reflecting the demands of contemporary software. By detailing our principled approach to benchmark selection, adaptation, and validation, we demonstrate how the SPEC CPU 2026 suite sets the standard for performance evaluation in the next era of computer architecture research and development.
Mahesh Madhav, Allen Lee, Andres Mejia, Branden Moore, Charan Soppadandi, Chris Cambly, Christoph Müllner, Daniel Bowers, David Reiner, Denis Bakhvalov, Duane Voth, Frédérique Silber-Chaussumier, James Bucek, James Southern, Jiangning Liu, Jim Himer, John Henning, Kristen Yang, Kunal Kashyap, Mason Guy, Mat Colgrove, Michael Berg, Prasad Battini, Prasad Joshi, Rohit Prasad, Shayantika Bhattacharya, Sriyash Caculo, Stefan Reimbold, Sundar Iyengar, Van Smith, Zarko Todorovski
ISCA32
1989 Computer aided design and built in self test on the i486TM CPU
abstract
The computer-aided design tools created to accelerate the design of the i486 CPU are described. Emphasis is on the logic synthesis, layout synthesis, and timing verification programs. The impact of the state-of-the-art tools on the project schedule is described, and the built-in self-test features on the processor are detailed. The type of advanced tools that will be required to design and test future processors, which will be more complex, is considered.>
Patrick P. Gelsinger, Sundar Iyengar, Joseph Krauskopf, James Nadir
ICCD2
1988 A Graphical Hardware Design Language
Paul J. Drongowski, Jwahar R. Bami, Ranganathan Ramaswamy, Sundar Iyengar, Tsu-Hua Wang
DAC4