EDBT 2026 Demo / reviewers in the wild / expert
Jya-Jang Tsai
dblp:96/4655
· DBLP profile ↗
2ranked-venue papers
0as first author
0since 2021 · last 1992
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2Software engineering, systems software and programming languages · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Performance modeling and evaluation · 86% Hardware accelerators and domain-specific architectures · 14% |
Topics — the 5 heaviest of 6, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Performance modeling and evaluation › simulation › discrete-event simulation › parallel discrete event simulation › optimistic simulation
time warp |
0.0 | 2 | 1992 | Design and Evaluation of the Rollback Chip: Special Purpose Hardware for Time Warp · IEEE Trans. Computers 1992 Design and Performance of Special Purpose Hardware for Time Warp · ISCA 1988 |
Performance modeling and evaluation › simulation › discrete-event simulation
parallel discrete event simulation |
0.0 | 1 | 1992 | Design and Evaluation of the Rollback Chip: Special Purpose Hardware for Time Warp · IEEE Trans. Computers 1992 |
Performance modeling and evaluation › simulation
discrete-event simulation |
0.0 | 1 | 1988 | Design and Performance of Special Purpose Hardware for Time Warp · ISCA 1988 |
Performance modeling and evaluation
simulation |
0.0 | 1 | 1992 | Design and Evaluation of the Rollback Chip: Special Purpose Hardware for Time Warp · IEEE Trans. Computers 1992 |
Performance modeling and evaluation › simulation › discrete-event simulation › parallel discrete event simulation
optimistic simulation |
0.0 | 1 | 1988 | Design and Performance of Special Purpose Hardware for Time Warp · ISCA 1988 |
Methods — techniques the papers use, named apart from their topics
simulation study · 0.0rollback algorithms · 0.0hardware state saving · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1992 | Design and Evaluation of the Rollback Chip: Special Purpose Hardware for Time WarpabstractExisting approaches to implement state saving are not appropriate for large Time Warp programs. The authors propose a component called the rollback chip (RBC) that efficiently implements state saving. Such a component could be used in a programmable, special purpose parallel discrete event simulation engine based on Time Warp. The algorithms implemented by the rollback chip are described, as well as mechanisms that allow efficient implementation. Results of simulation studies are presented that show that the rollback chip can virtually eliminate the state saving and rollback overheads that plague current software implementations of Time Warp.> Richard M. Fujimoto, Jya-Jang Tsai, Ganesh Gopalakrishnan |
IEEE Trans. Computers | 2 |
| 1988 | Design and Performance of Special Purpose Hardware for Time WarpabstractA special-purpose simulation engine based on the Time Warp mechanism is proposed to attack large-scale discrete-event simulation problems. A key component of this engine is the rollback chip, a hardware component that efficiently implements state saving and rollback functions in Time Warp. The algorithms implemented by the rollback chip are described, as well as mechanisms that allow efficient implementation. Results of simulation studies are presented that show that the rollback chip can virtually eliminate the state-saving overhead that plagues current software implementations of Time Wrap.> Richard M. Fujimoto, Jya-Jang Tsai, Ganesh Gopalakrishnan |
ISCA | 2 |