The rapid pace of innovation in electronics, driven by advancements in computing, machine learning, and artificial intelligence, has created an unprecedented demand for more efficient and powerful computing platforms. As integrated circuits (ICs) continue to scale and integrate into increasingly complex systems, they consume more power, leading to significant challenges in power integrity. These challenges are further exacerbated by the growing complexity of modern IC designs, necessitating more intelligent and actionable approaches to ensure robust power delivery networks.

Early-stage, microarchitecture-level power modeling methodologies have been used in industry and academic research for a decade (or more). Such methods use cycle-accurate performance simulators and deduce active power based on utilization markers. A key question faced in this context is: what key utilization metrics to monitor, and how many are needed for accuracy? Is there a systematic way to select the “best” markers? We also pose a key follow-on question: is it possible to perform accurate scaling of an abstracted model to enable exploration of new microarchitecture features? In this paper, we address these particular questions and examine the results for a range of abstraction levels. We highlight innovative insights for intelligent abstraction and microarchitecture scaling, and point out the pitfalls of abstractions that are not based on a systematic methodology or sound theory.

In this paper, we propose a new technique, referred to as virtual probe (VP), to efficiently measure, characterize, and monitor spatially-correlated inter-die and/or intra-die variations in nanoscale manufacturing process. VP exploits recent breakthroughs in compressed sensing to accurately predict spatial variations from an exceptionally small set of measurement data, thereby reducing the cost of silicon characterization. By exploring the underlying sparse pattern in spatial frequency domain, VP achieves substantially lower sampling frequency than the well-known Nyquist rate. In addition, VP is formulated as a linear programming problem and, therefore, can be solved both robustly and efficiently. Our industrial measurement data demonstrate the superior accuracy of VP over several traditional methods, including 2-D interpolation, Kriging prediction, and k-LSE estimation.

In this paper, we propose a new technique, referred to as Multi-Wafer Virtual Probe (MVP) to efficiently model wafer-level spatial variations for nanoscale integrated circuits. Towards this goal, a novel Bayesian inference is derived to extract a shared model template to explore the wafer-to-wafer correlation information within the same lot. In addition, a robust regression algorithm is proposed to automatically detect and remove outliers (i.e., abnormal measurement data with large error) so that they do not bias the modeling results. The proposed MVP method is extensively tested for silicon measurement data collected from 200 wafers at an advanced technology node. Our experimental results demonstrate that MVP offers superior accuracy over other traditional approaches such as VP and EM, if a limited number of measurement data are available.

Static Random Access Memories (SRAMs) are key components of modern VLSI designs and a major bottleneck to technology scaling as they use the smallest size devices with high sensitivity to manufacturing details. Analysis performed at the "schematic" level can be deceiving as it ignores the interdependence between the implementation layout and the resulting electrical performance. We present a computational framework, referred to as "Virtual SRAM Fab", for analyzing and estimating pre-Si SRAM array manufacturing yield considering both lithographic and electrical variations. The framework is being demonstrated for SRAM design/optimization in 45nm nodes and currently being used for both 32nm and 22nm technology nodes. The application and merit of the framework are illustrated using two different SRAM cells in a 45nm PD/SOI technology, which have been designed for similar stability/performance, but exhibit different parametric yields due to layout/lithographic variations. We also demonstrate the application of Virtual SRAM Fab for prediction of layout-induced imbalance in an 8T cell, which is a popular candidate for SRAM implementation in 32-22nm technology nodes.

Nanoscale device characteristics and noise coupling have rendered traditional waveform-based gate delay models increasingly difficult to adopt. While the widely adopted delay models are built upon the assumption of simple ramp-like signal waveforms, realistic signal shapes in nanoscale designs can be far more complex. The need for considering process-voltage-temperature (PVT) variations imposes further accuracy requirement on gate models. We present a parameterizable waveform independent gate model (PWiM) where no assumption is made upon the input waveforms. The PWiM model is constructed by encapsulating the driver's intrinsic nonlinear dc and dynamic characteristics, which are important to model for complex signal waveforms, via novel and yet easy-to-implement characterization steps. As such, PWiM can provide near-SPICE accuracy for input signals that significantly deviate from simple ramps. While recently developed current-based models can only be applied to single channel-connected component, PWiM can work for multistage cells leading to improved library compactness and analysis efficiency. Our experiments have indicated that the proposed driver model not only provides up to two orders of magnitude speedups over SPICE for delay and noise analysis, it also offers accurate assessment of performance variability introduced by process and environmental variations.

Leakage is an important performance bottleneck in current digital integrated circuit technology. Many techniques were proposed to analyze, control and avoid leakage of a circuit, but all efforts need accurate characterizations of total leakage variations of a chip under real-life manufacturing and environmental parameter fluctuations. In this paper, we are proposing to apply a new statistical technique to model the overall distribution of total chip leakage under such variations. With our proposed model, chip designers and design automation tools can better assess and manage leakage power

The simulation of circuits containing silicon-on-insulator (SOI) transistors encounters specific difficulties mainly due to the presence of the insulated body nodes, i.e., connected by high impedance connections with the rest of the circuit. These high impedance connections cause the charges stored in transistor body nodes to change at much slower rates than the normal operation of the circuit. Therefore the short term operation of a circuit will be strongly dependent on the state of the SOI transistor body charge, which in turn depends on the activity of the transistor during thousands of the previous cycles: the history effect. The presence of high impedance connections has another adverse effect on the simulation of such circuits: circuit matrices become severely ill-conditioned, thus slowing down or even compromising the convergence of the initial DC solution. In this paper, we are introducing the novel non-equilibrium, initial condition analysis (NEICA), as the preferred initialization method for circuits containing SOI devices. This method allows the user full control of the initial state of the SOI devices, preserves full insight into the physical phenomenon, and leads to a well-conditioned and thus reliable transient analysis initialization problem. The method is easily implemented in most existing circuit simulation programs and facilitates other important applications beyond the analysis of SOI transistor circuits. ESD analysis, and simulation of the effects of charged particles hitting circuits, are just two such examples

Technology scaling and the push for ever increased performance has resulted in the rapid increase of integrated circuit power dissipation. We are already in the era of the 100 Watt IC (Diefendorff, 1999). This necessitates the detailed modeling and analysis of the on-chip power distribution for robustness and reliability (Chen and Ling, 1997). An important component of this model is the decoupling capacitance of the design which includes dedicated decoupling capacitors as well as the capacitance of non-switching circuits. This paper describes a technique for modeling the decoupling capacitance of circuits. An exact simulation-based method is outlined, and fast yet accurate analytical models are proposed

In nanoscale regime, it is becoming increasingly difficult to model signal shapes using simple ramp-like waveforms due to various noise coupling effects. We present an accurate waveform independent gate (WiM) model without any assumption of signal waveforms. Our model can be applied to arbitrary gate inputs while maintaining excellent near-SPICE accuracy. The application of the proposed gate modeling technique is demonstrated under the context of the gate-level timing simulation.

Abstract − Power dissipation is becoming a major show stopper for integrated circuit design especially in the server and pervasive computing technologies. Careful consideration of power requirements is expected to bring major changes in the way we design and analyze integrated circuit performance. This paper proposes a practical methodology to evaluate the short−circuit power of static CMOS gates via effective use of timing information from timing analysis. We introduce three methods to estimate short−circuit power of a static CMOS circuit without requiring explicit circuit simulation. Our proposed methodology offers practical advantages over previous approaches, which heavily rely on simple special device models. Proposed approach is experimented with an extensive set of benchmark examples and several device models and found very accurate. I.

With the scaling of technology, power grid noise is becoming increasingly significant for circuit performance. A typical power grid circuit contains millions of linear elements, making noise analysis and verification challenging in terms of both run time and memory. We propose a power grid reduction scheme based on algebraic multigrid principles, in which the coarser-level grid and the restriction operators are constructed automatically from the circuit matrices. This method is suitable for large-scale power grid transient and AC analysis. Experimental results show an order of magnitude speed-up over flat analysis in addition to practical tradeoffs for accuracy, CPU time and memory usage.

Leakage power is emerging as a new critical challenge in the design of high performance integrated circuits. Leakage is increasing dramatically with each technology generation and is expected to dominate system power. This paper describes a static (i.e input independent) technique for efficient and accurate leakage estimation. A probabilistic technique is presented to compute the average leakage of combinational circuits. The proposed technique gives accurate results with an average error of only 2% for the ISCAS benchmarks and accurately predict both subthreshold and gate leakage as well as the leakage sensitivities to process and environmental parameters.

Leakage power is emerging as a key design challenge in current and future CMOS designs. Since leakage is critically dependent on operating temperature and power supply, we present a full chip leakage estimation technique which accurately accounts for power supply and temperature variations. State of the art techniques are used to compute the thermal and power supply profile of the entire chip. Closed-form models are presented which relate leakage to temperature and VDD variations. These models coupled with the thermal and VDD profile are used to generate an accurate full chip leakage estimation technique considering environmental variations. The results of this approach are demonstrated on large-scale industrial designs.

The relative tolerances for interconnect and device parameter variations have not scaled with feature sizes which have brought about significant performance variability. As we scale toward 10 nm technologies, this problem will only worsen. New circuit families and design methodologies will emerge to facilitate construction of reliable systems from unreliable nanometer scale components. Such methodologies require new models of performance which accurately capture the manufacturing realities. Recently, one step toward this goal was made via a new variational reduced order interconnect model that efficiently captures large scale fluctuations in global parameter values. Using variational calculus the linear interconnect systems are represented by analytical models that include the global variational parameters explicitly. In this work we present a framework which extends the previous work to a linear-centric simulation methodology with accurate nonlinear device models and their fluctuations. The framework is applied to generate path delay distributions under nonlinear and linear parameter fluctuations.

Static timing analysis breaks down the longest path problem into waveform analysis of paths of logic stages that are comprised of nonlinear transistors and complex RLC loads. Runtime efficiency is of the utmost importance; however, the waveform evaluation of these logic stages cannot be accelerated via timing simulation algorithms that attempt to exploit temporal or spatial latency since the simulation problem is already a partitioned one. TETA was developed as a general purpose transistor-level waveform evaluation engine for providing accuracy-efficiency tradeoffs for these logic-stage waveform evaluation problems that are encountered during timing analysis. Of particular emphasis are the large RC(L) coupled logic stages which present the bottleneck for waveform evaluation along multiple stages of a digital circuit path. TETA applies a novel compaction scheme for the logic-stage transistor clusters and employs a novel nonlinear algebraic solution method to analyze the circuit. Importantly, stability of the waveform evaluation with TETA requires only stable single-input multi-output N-port interconnect models that are not necessarily passive. Waveform evaluators that use general transistor and piecewise linear device models require provably passive multi-input multi-output interconnect models that can be extremely inefficient for large coupled N-port problems. Furthermore, the methodology in TETA brings extra efficiency by avoiding extra matrix factorizations and enabling the use of device model tables without any loss of accuracy. Complex logic gates and nonlinear capacitors are handled without loss of generality.

The Elmore delay is the metric of choice for performance-driven design applications due to its simple, explicit form and ease with which sensitivity information can be calculated. However, for deep submicron technologies, the accuracy of the Elmore delay is insufficient. In this paper we formulate a delay model using a provably stable two pole waveform response that provides a unique mapping between four moments and a specific delay value. Unlike traditional moment matching, this two-pole model permits us to precharacterize the delays, and store them in a table, as a mapped function of three parameters. The model also provides an explicit expression for the peak noise induced on a coupled line as a function of the same three moments. The results indicate runtimes comparable to an Elmore delay calculation but with the accuracy of an AWE approximation.

To take advantage of fast converging multi-channel recursive least squares algorithms, we propose an adaptive IIR system structure consisting of two parts: a two-channel FIR adaptive filter whose parameters are updated by the rotation-based multi-channel least squares lattice (QR-MLSL) algorithm, and an adaptive regressor which provides more reliable estimates to the original system output based on previous values of the adaptive system output and noisy observation of the original system output. Two different regressors are investigated and robust ways of adaptation of the regressor parameters are proposed. Based on extensive set of simulations, it is shown that the proposed algorithms converge faster to more reliable parameter estimates than LMS type algorithms.

Recently a probability interpretation of moments wm proposed as a compromise between the Elmore delay and higher or&r mommt matching for RC timing estimation [5].By modeling RC impufses as tinze-sht~ed incomplete gamma distribution functions, the delays could be obtained via table 100tip using a gamma integral table and the first three moments of the imptise response.However, while this approximation worti well for many examples, it struggles with responses when the metal resistance becomes dominant, andproduces results with impractical h.meshz~values.In this paper the probability interpretation is etiended to the circuit homogeneous response, without requiring the time shi$ parameter The gamma distribution is used to characterize the normalized homogeneous portion of the step response.For a generalized RC interconnect model (RC tree or mesh), the stability of the holtlogetleol{s-gml?ta distribution model is guaranteed.It is demonstrated that when a table model is carefilly constructed the hgamma approxinrationprovides for exellent improvemeti over the Elmore delay in terms of accur~, with ve~little additiond cost in terms of CPU time.