Low power system-on-chips (SoCs) are now at the heart of Internet-of-Things (IoT) devices, which are well-known for their bursty workloads and limited energy storage-usually in the form of tiny batteries. To ensure battery lifetime, dynamic voltage frequency scaling (DVFS) has become an essential technique in such SoC chips. With continuously decreasing supply level, noise margins in these devices are already being squeezed. During DVFS transition, large current that accompanies the clock speed transition runs into or out of clock networks in a few clock cycles, induces large Ldi/dt noise, thereby stressing the power delivery system (PDS). Due to the limited area and cost target, adding additional decoupling capacitance to mitigate such noise is usually challenging. A common approach is to gradually introduce/remove the additional clock cycles to increase/decrease the clock frequency in steps, also known as, clock skipping. However, such a technique may increase DVFS transition time, and still cannot guarantee minimal noise. In this paper, we propose a new noise-aware DVFS sequence optimization technique by formulating a mixed 0/1 programming to resolve the problems of clock skipping sequence optimization. Moreover, the method is also extended to schedule extensive wake-up activities on different clock domains for the same purpose. The experiments show that the optimized sequence is able to significantly mitigate noise within the desired transition time, thereby saving both power and energy.

Low power system-on-chips (SoCs) are now at the heart of Internet-of-Things (IoT) devices, which are well known for their bursty workloads and limited energy storage --- usually in the form of tiny batteries. To ensure battery lifetime, DVFS has become an essential technique in such SoC chips. With continuously decreasing supply level, noise margins in these devices are already being squeezed. During DVFS transition, large current that accompanies the clock speed transition runs into or out of clock networks in a few clock cycles, and induces large Ldi/dt noise, thereby stressing the power delivery network (PDN). Due to the limited area and cost target, adding additional decap to mitigate such noise is usually challenging. A common approach is to gradually introduce/remove the additional clock cycles to increase or reduce the clock frequency in steps, a.k.a., clock skipping. However, such a technique may increase DVFS transition time, and still cannot guarantee minimal noise. In this work, we propose a new noise-aware DVFS sequence optimization technique by formulating a mixed 0/1 programming to resolve the problems of clock skipping sequence optimization. Moreover, the method is also extended to schedule extensive wake-up activities on different clock domains for the same purpose. The results show that we are able to achieve minimal-noise sequence within desired transition time with 53% noise reduction and save more than 15--17% power compared with the traditional approach.

Power integrity has become increasingly important for sub-32nm designs. Many prior works have discussed power grid design and optimization in the post-layout stage, when design change is inevitably expensive and difficult. In contrast, during the early stage of a development cycle, designers have more flexibility to improve the design quality. However, there are several fundamental challenges at early stage when the design database is not complete, including extraction, modeling, and optimization. This article tackles these fundamental issues of early-stage power grid design from architecture to layout. The proposed methods have been silicon validated on 32nm on-market chips and successfully applied to a 22nm design for its early-stage power grid design. The findings from such practices reveal that, for sub-32nm chips, an intrinsic on-die capacitance and power gate scheme may have more significant impact than expected on power integrity, and needs to be well addressed at early stage.

Many prior works have discussed the power grid design and optimization in the post-layout stage, when design change is inevitably expensive and difficult. In contrast, during the early stage of a development cycle, designers have more flexibility to improve the design quality. However, there are several fundamental challenges at early-stage when design database is NOT complete, including extraction, modeling and optimization. This paper tackles these fundamental issues of early-stage power grid design. The proposed methods have been silicon-validated on 32nm on-market chips and successfully applied to a 22nm design for its early stage power grid design. The findings from such practices reveal that, for sub-32nm chips, intrinsic on-die capacitance and power gate scheme may have more significant impact than expected on power integrity, and need to be well addressed at early stage.

This paper proposes a fast and high-capacity electromagnetic solution, time-domain layered finite element reduction recovery (LAFE-RR) method, for high-frequency modeling and simulation of large-scale on-chip circuits. This method rigorously reduces the matrix of a multilayer system to that of a single-layer one regardless of the original problem size. More important, the matrix reduction is achieved analytically, and hence the CPU and memory overheads are minimal. The recovery of solutions in all other layers involves only forward and backward substitution of matrices of single-layer size. The memory cost is also modest-requiring only the memory needed for the factorization of a single layer sparse matrix. The improved performance applies to any arbitrarily shaped multilayer structure. Numerical and experimental results are presented to demonstrate the accuracy, efficiency, and capacity of the proposed method.