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Ming-Chuen Shiau

dblp:96/4928 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 1990
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 70% Integrated circuit design · 30%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Integrated circuit design
digital circuit design		 0.011990
Efficient physical timing models for CMOS AND-OR-inverter and OR-AND-inverter gates and their applications · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1990
Electronic design automation › physical design
gate sizing		 0.011990
Efficient physical timing models for CMOS AND-OR-inverter and OR-AND-inverter gates and their applications · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1990
Electronic design automation
physical design		 0.011990
Efficient physical timing models for CMOS AND-OR-inverter and OR-AND-inverter gates and their applications · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1990
Electronic design automation
timing analysis		 0.011990
Efficient physical timing models for CMOS AND-OR-inverter and OR-AND-inverter gates and their applications · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1990

Methods — techniques the papers use, named apart from their topics

SPICE simulation · 0.0
YearPublicationVenuePosition
1990 Efficient physical timing models for CMOS AND-OR-inverter and OR-AND-inverter gates and their applications
abstract
Efficient physical timing models for complex CMOS AND-OR-inverter (AOI) and OR-AND-inverter (OAI) gates have been successfully developed. Through extensive comparisons with SPICE simulation results, the developed models have shown a maximum error of 30% for long-channel and small-geometry CMOS AOI/OAI gates with wide ranges of channel dimensions, capacitive loads, logic input patterns, circuit configurations, device parameter variations, and noncharacteristic waveform input excitations. The error can be further reduced to 16% with the commonly used device dimensions. The developed timing models are successfully applied to the autosizing of CMOS AOI/OAI gates. The results show a good accuracy and a reasonable CPU time consumption.>
Chung-Yu Wu, Ming-Chuen Shiau
 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.2