FPGAs (Field programmable Gate Arrays) are useful compo-nents for embedded systems. In combination with Systems-on-Chip and Networks-on-Chip they enable flexible system solutions. Reliability and fault tolerance in such systems often is implemented by adding components for redundancy. Due to constraints in structural resources of FPGA chips, this approach in many cases does not provide adequate solutions. Indirect re-dundancy combined with universal component monitoring is a solution for failsafe Systems-on-Chip / Networks-on-Chip appli-cations in such situations.

To transform a systematic model of project management (PM) into a powerful discrete event model (DEM), these two concepts must be merged for mapping and simulation. To achieve this the modeling of PM, its complex tasks must be abstracted, and a decomposition of the entire model into subsystems including the interactions and their components has to be carried out. A merge can only take place if a common level of detailing and abstraction can be identified. In a DEM, the complexity is put into the connection of the subsystems. The behavior of the individual subsystems, however, is kept simple.[1].

Faster development of new algorithms is crucial in modern projects. Highly abstracted, data flow and modular oriented model-driven development methods and tools are used for this purpose. But with higher abstraction levels, there is always an increase in runtime overhead and a reduction in performance. Especially in real-time and cost-sensitive applications, this becomes a big issue that has to be dealt with. In this paper, we present a data flow and model-driven Matlab/Simulink plugin for generating efficient assembly code for a specialized hard real-time softcore processor. In this context, different optimization approaches will be introduced that are minimizing the overhead that comes with the used abstraction level. It will be shown that with the developed mechanisms, it is possible to generate assembly code nearly without any abstraction overhead and reducing the development time of any new algorithm by re-using pre-constructed modular parts.

The increasing complexity of the business processes requires automated methods for trouble-shooting and debugging of the process model in operation. This paper proposes mechanism of fault detection based on the concept of backwards reachability for the coloured workflow nets. The formal verification methods defined for coloured Petri nets such as state space method or place invariants declaration suffer from fast-growing computational complexity. The article offers the set of firing rules for backwards token-play on coloured workflow net. This method helps to detect resource-related failures of the two most common types: ”the missing arc” fault (the resource was not initialized) and ”wrong expression fault” (there is no proper resource).

The design of complex distributed automation systems often presents great challenges due to the size and number of components which have to work in parallel to one another in real time. This paper discusses some of the problems of designing such systems. The use of colored dynamic state diagrams for the modeling of complex real-time systems is suggested as a possible solution. This type of diagram is based on State Charts, the well-known and generally applied description technique included as one variation in the unified modeling language. Colored State Charts harness two techniques: the modelling technique well accepted by engineers, and high level Petri nets with their outstanding powers of description. By coloring State Charts, the behaviour of several objects or processes can be modelled simultaneously in a single figure. The colored state diagrams contain a variety of resources to facilitate clear and unequivocal representation of the composition of a number of simple state diagrams. They also have additional mechanisms for mapping the dependencies and relationships between individual objects. Via transformation into colored Petri nets, they make formal verification possible. Their usability is shown in a modelled reference example.

This paper aims at the development of an engineering technique for the construction of systems through the refinement of duration interval transitions. The theoretical system model is based on so-called interval time Petri nets. Duration interval transitions turn out to be a syntactical abbreviation for a certain structure of interval time Petri nets. The kind of refinement technique preserves the safety property and guarantees that the refined system behaves neither slower nor faster than the unrefined one. The application of our approach lies in the development of time correct system specifications.