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Michael Eick

dblp:96/513 · DBLP profile ↗
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4ranked-venue papers
3as first author
0since 2021 · last 2012
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 4 · 3 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Electronic design automation · 100%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation
analog circuit design automation
0.322012
MARS: Matching-Driven Analog Sizing · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2012
Comprehensive Generation of Hierarchical Placement Rules for Analog Integrated Circuits · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2011
Electronic design automation › physical design › placement › circuit placement
analog placement
0.322012
MARS: Matching-Driven Analog Sizing · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2012
Comprehensive Generation of Hierarchical Placement Rules for Analog Integrated Circuits · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2011
Electronic design automation › circuit sizing
analog circuit sizing
0.112012
MARS: Matching-Driven Analog Sizing · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2012
Electronic design automation › analog circuit design automation
symmetry-constraint generation
0.112012
MARS: Matching-Driven Analog Sizing · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2012

Methods — techniques the papers use, named apart from their topics

qualitative signal flow analysis · 0.1numerical optimization · 0.1structural signal flow graph · 0.1hierarchical partitioning · 0.1
YearPublicationVenuePosition
2012 MARS: Matching-Driven Analog Sizing
abstract
This paper presents a new approach for automatic computation of matching constraints for analog sizing. The method automatically analyzes a circuit netlist to generate sizing constraints. These sizing constraints are considered during a subsequent numerical optimization. It is the first method that computes symmetry constraints for sizing, based on the hierarchical structure of the circuit and a qualitative signal flow. As a unique feature, the method is capable of handling multiple signal and feedback paths, leading to multiple symmetry axes. It can be applied to linear and nonlinear circuits and any available sizing algorithm. Experimental results show that the runtime of analog sizing, as well as of result quality, are greatly improved.
Michael Eick, Helmut E. Graeb
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.1
2011 Comprehensive Generation of Hierarchical Placement Rules for Analog Integrated Circuits
abstract
This paper presents a new method to automatically generate hierarchical placement rules, which are crucial for a successful analog placement. The method is based on a novel symmetry computation method, introducing the structural signal flow graph. Five types of proximity, matching and symmetry constraints are determined. According to the priority of the constraint types, a constraint requirement graph and a hierarchical partitioning of the circuit into matching, proximity and symmetry groups is then automatically computed. Based on experimental results with a state-of-the-art placement tool, we show that the new approach generates more placement rules and can lead to better circuit performance and parametric yield according to post-layout simulation.
Michael Eick, Martin Strasser, Kun Lu 0005, Ulf Schlichtmann, Helmut E. Graeb
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.1
2010 Automatic generation of hierarchical placement rules for analog integrated circuits
abstract
This paper presents a new method to automatically generate hierarchical placement rules, which are crucial for a successful analog placement.
Michael Eick, Martin Strasser, Helmut E. Graeb, Ulf Schlichtmann
ISPD1
2008 Deterministic analog circuit placement using hierarchically bounded enumeration and enhanced shape functions
abstract
The analog placement algorithm Plantage, presented in this paper, generates placements for analog circuits with comprehensive placement constraints. Plantage is based on a hierarchically bounded enumeration of basic building blocks, using B*-trees. The practically relevant solution space is thereby enumerated quasi-complete. The sets of possible placements of the basic building blocks are represented and combined in a new efficient way, using enhanced shape functions. The result of Plantage is the Pareto front of placements with respect to different aspect ratios. The whole approach is deterministic, in contrast to existing analog placement algorithms.
Martin Strasser, Michael Eick, Helmut E. Graeb, Ulf Schlichtmann, Frank M. Johannes
ICCAD2