Instruction-level parallelism (ILP) processors have been widely used to improve speed for several decades. However, the requirement of parallelism changes between applications, even within an application. Fixed high parallelism could result in poor utilization and extra leakage energy. Designing energy-efficient ILP processors to trade off power/speed has been a critical issue in current research. In this paper, a compiler-guided parallelism adaption based on an application partition algorithm is proposed to implement parallelism adaption with applications running on ILP processors. The aim is to minimize energy consumption without degrading the execution time. The main idea is described as follows: 1) partition the application into several power gating regions (PGRs); 2) assign adapted parallelism for each region by analyzing the requirements of resources and energy efficiency; and 3) reschedule each region with its own parallelism and insert power-gating instructions into the application to control hardware ON/OFF. The experimental results of evaluation with the CoreMarkPro benchmark suits show the expected savings of leakage energy. Our algorithm could reduce the leakage energy in register files by 30.46% and 64.06% for applications with high variance on software-inherent parallelism. Furthermore, the overhead energy originated from state transition is much lower than Tabkhi's algorithm.

Designing energy-efficient Digital Signal Processor (DSP) cores has become a key concern in embedded systems development. This paper proposes an energy-proportional computing scheme for Very Long Instruction Word (VLIW) architectures. To make the processor power scales with adapted parallelism, we propose incorporating distributed Power-Gated Register Files (PGRF) into VLIW to achieve a PGRF-VLIW architecture. For energy efficiency, we also propose an instruction scheduling algorithm called the Deadline-Constrained Clustered Scheduling (DCCS) algorithm. The algorithm clusters the data dependence graph to reduce data transfer energy and makes optimal use of low-powered local registers for tree-structured data dependence graphs. The results of evaluations conducted using the MiBench and DSPstone benchmark suites substantiate the expected power saving and scaling effects.