Demo Data from EDBT 2026 / reviewers in the wild / expert
Thomas Baumann
dblp:96/6045
· DBLP profile ↗
2ranked-venue papers
2as first author
0since 2021 · last 2012
—ORCID · unresolved
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2 · 2 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Integrated circuit design · 44% Hardware reliability and fault tolerance · 44% Embedded and real-time systems · 13% |
Topics — the 2 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Integrated circuit design
low-power circuit design |
0.1 | 1 | 2009 | Architectural assessment of design techniques to improve speed and robustness in embedded microprocessors · DAC 2009 |
Embedded and real-time systems › embedded processor
embedded microprocessor |
0.0 | 1 | 2009 | Architectural assessment of design techniques to improve speed and robustness in embedded microprocessors · DAC 2009 |
Methods — techniques the papers use, named apart from their topics
pulsed latch design · 0.1multi-stage static timing analysis · 0.1
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2012 | Parallel Parameter Identification in Industrial BiotechnologyabstractReal-valued black-box optimization of badly behaved and not well understood functions is a wide topic in many scientific areas. Possible applications range from maximizing portfolio profits in financial mathematics over efficient training of neuronal networks in computational linguistics to parameter identification of metabolism models in industrial biotechnology. This paper presents a comparison of several global as well as local optimization strategies applied to the task of efficiently identifying free parameters of a metabolic network model. A focus is being set on the ease of adopting these strategies to modern, highly parallel architectures. Finally an outlook on the possible parallel performance is being presented. Thomas Baumann, Michael M. Resch |
ISPA | 1 |
| 2009 | Architectural assessment of design techniques to improve speed and robustness in embedded microprocessorsabstractThis work investigates the interrelation of performance and robustness against variability in industrial microprocessor designs. A novel analysis technique for variation-sensitive hardware and two figures of merit to quantify the robustness of a design against variations are proposed. Together with a multi-stage STA this enables an efficient application of low-V T cell insertion and pulsed latch design to compensate for within-die delay variations. For the same speed margin of 5% on design level, a pulsed latch design of an ARM926 microprocessor shows a 2.5× higher robustness compared to a MS-FF design with selective low-V T cell insertion. Thomas Baumann, Doris Schmitt-Landsiedel, Christian Pacha |
DAC | 1 |