To address the problem of accurate timing characterization, this paper proposes a method that fully exploits mode dependency. It is based on the premise that circuit delays are determined largely by a set of control inputs for which the number of useful combinations, i.e., modes, is small for most practical circuits. We take the mode-dependent characterization approach further and enhance it so that the delays of the I/O paths between the control inputs and outputs are calculated more accurately. We prove that, with a careful choice of propagation conditions, our method can generate timing models with very tight path delays that are guaranteed to give correct results. Experimental results using real-life circuits show that cir-cuit delays can vary significantly among different modes for both control and data input delays, and capturing this variation can have a significant impact on the overall system timing.

In deep submicrometer integrated circuit design, there is a growing need to quickly and accurately characterize the timing of large circuit blocks. Accurate timing characterization requires making available as much timing information as possible at each step of the design process. Conventional fast characterization methods typically employ topological analysis, which can be inaccurate because of its inability to eliminate false paths. To address this problem, a new method for creating accurate timing models of circuit blocks by making efficient use of their functionality is introduced. The proposed mode-dependent characterization (ModeChar) method is based on calculating a distinct timing model for each mode of circuit operation and reflects the way practical circuits function. ModeChar produces a mode-dependent timing model that contains delay information for a given set of circuit modes. It is shown that circuit delays are never underestimated by the mode-dependent models. The concept of mode dependency is taken further by extending it to sequential circuits. Given a sequential circuit, a compact set of constraints is derived for each circuit mode that captures all the timing constraints that must be satisfied for correct operation of the circuit. Experimental results are presented that demonstrate the effectiveness of ModeChar in eliminating many false paths that would otherwise result in performance penalties. In addition, our experiments indicate that delays can vary considerably among circuit modes, making conventional topological analysis overly pessimistic. To make the mode-dependent models more compact, an efficient algorithm far coalescing delay information is also introduced.

A high accuracy system for transistor-level static timing analysis is presented. Accurate static timing verification requires that individual gate and interconnect delays be accurately calculated. At the sub-micron level, calculating gate and interconnect delays using delay models can result in reduced accuracy. Instead, the proposed method calculates delays through numerical integration using an embedded circuit simulator. It takes into account short circuit current and carefully chooses the set of conditions that results in a tight upper bound of the worst case delay for each gate. Similar repeating transistor configurations of gates in the circuit are automatically identified and a novel interpolation based caching scheme quickly computes gate delays from the delays of similar gates. A tight object code level integration with a commercial high speed transistor level circuit simulator allows efficient invocation of the simulation.

A method that characterizes the timing of Intellectual Property (ZP) blocks while taking into account IP functionality is presented.IP blocks are assumed to have multiple modes of operation specified by the user.For each mode, our method calculates IO path delays and timing constraints to generate a timing model.The method thus captures the mode-dependent variation in IP delays which, according to our experiments, can be as high as 90%.The special manner in which delay calculation is performed guarantees that IP delays are never underestimated.The resulting timing models are also compacted through a process whose accuracy is controlled by the user.1.1

Accurate and efficient computation of delays is a central problem in computer-aided design of complex VLSI circuits. Delays are determined by events (signal transitions) propagated from the inputs of a circuit to its outputs, so precise characterization of event propagation is required for accurate delay computation. Although many different propagation conditions (PCs) have been proposed for delay computation, their properties and relationships have been far from clear. We present a systematic analysis of delay computation based on a series of waveform models that capture signal behavior rigorously at different levels of details. The most general model, called the exact of W0 model, specifies each event occurring in a circuit signal. A novel method is presented that generates approximate waveforms by progressively eliminating signal values from the exact model. For each waveform model, we drive the PCs that correctly capture the requirements under which an event propagates along a path. The waveform models and their PCs are shown to form a well-defined hierarchy, which provides a means to trade accuracy for computational effort. The relationships among the derived PCs and existing ones are analyzed in depth. It is proven that though many PCs, such as the popular floating mode condition, produce a correct upper bound on the circuit delay, they can fail to recognize event propagation in some instances. This analysis further enables us to derive new and useful PCs. We describe such a PC, called safe static. Experimental results demonstrate that safe static provides an excellent accuracy/efficiency tradeoff.

We present a novel timing analysis method ACD that computes an approximate value for the delay of datapath circuits. Based on the conditional delay matrix (CDM) formalism we introduced earlier the ACD method exploits the fact that most datapath signals are directed by a small set of control inputs. The signal propagation conditions are restricted to a set of predefined central inputs, which results in significant reductions in the size of the conditions as well as computation time. We have implemented ACD and experimented with reverse-engineered high-level versions of the ISCAS-85 benchmarks. Our results demonstrate up to three orders of magnitude speedup in computation time over exact methods, with little or no loss in accuracy.

We present a novel method to perform timing analysis of hierarchical circuits. It is based on the representation of circuit modules by conditional delay matrices (CDMs) which combine module delays with event propagation conditions. The CDM model is independent of module complexity and allows automatic identification of false paths. We exploit hierarchy information to perform efficient delay computation. The effectiveness of the method is demonstrated on a high-level model of the ISCAS-85 circuit c6288, which is difficult to analyze using traditional approaches. The method has been implemented in a symbolic timing analysis program called CAT. The application of CAT to carry-skip adders shows that hierarchical timing analysis is faster by an order of magnitude than gate-level analysis.