Time-Sensitive Network (TSN) has been considered one of the most viable solutions to meet the increasing demands for ultra-low latency in the 5G and post-5G eras. Due to the importance of timing constraints, network measurement tools are necessary for TSN research and operations to evaluate the performance limits of proofs-of-concept, troubleshoot failures, etc. However, current measurement solutions struggle to achieve important aspects of TSN networks, such as precise control of the transmission frame intervals and burst sizes. Additionally, they cannot generate a mix of multiple flows of various characteristics. In this paper, we present Ethernet Frame Crafter & Capture (EFCC), an FPGA-based network measurement tool to address the aforementioned issues. The proposed system allows the frame generation/capture functions to be configured independently for each port at a line rate of 1GbE. Furthermore, EFCC is open-source and can be ported to most commodity FPGA boards available in the market. The evaluation results demonstrate that the proposed frame generator allows the mixing of multiple flows of various characteristics and that the frame capture module can record the transmit and receive timestamps of frames with a precision of 8-ns/6.4-ns.

Time Sensitive Network (TSN) is one of the most auspicious solutions to respond to the increasing demands in ultra-low latency in the 5G and post-5G eras. It comes as an extension to the conventional IEEE 802.3 Ethernet networks by adding a set of novel open standards that aims to provide deterministic, reliable, high-bandwidth, and low-latency communication. In this paper, we present an open-source and light-weight FPGA-based network switch design and implementation supporting Credit Based Shaper (CBS) for Time Sensitive Networks. We present the key design components and implementation aspects of the proposed switch and discuss the preliminary evaluation results in a fair amount of detail to validate our proposal. The conducted experiments show that the proposed switch properly shapes the traffic by eliminating bursts in irregular traffic and efficiently forwards prioritized traffic as stipulated by the TSN requirements. In addition, we demonstrate that our hardware latency evaluation results conform with the CBS theoretical model and that the proposed switch consumes a very reasonable portion of the hardware resources on an affordable FPGA.

The combination of neuromorphic computing (NC) and 3-D integrated circuits - the 3-D stacking neuromorphic system can be the most advanced architecture that inherits the benefits of both computing and interconnect paradigms. However, simply shifting to the third dimension cannot exploit the 3-D structure and also end up with a low yield rate issue. Therefore, in this article, we propose a methodology to design 3-D stacking synaptic memory for power-efficient operations and yield rate improvement of neuromorphic systems. In this proposed methodology, the synaptic weights are stacked on top of the processing elements (PEs), and these weights are split into multiple subsets placed in different layers. Furthermore, with the support of 3-D technology, the supply voltage of each layer can be controlled independently which leads to power reduction by scaling down or turning off the supply voltage of the memory layer(s) containing the least significant bits (LSBs) while maintaining acceptable accuracy. On top of that, this work also proposes a methodology to deal with the low yield rate issue by treating the defective memory cells as noises. In our evaluation with the CMOS 45 nm technology, the energy per synaptic operation (SOP) for MNIST classification, when undervolting two upper memory layers (from 1.1 to 0.8 V), reduces by 21.62% while the accuracy only reduces sightly by 0.51%. This energy reduction increases to 66.77% with 6.58% accuracy loss when our system uses both power-gating and undervolting for all memory layers. Furthermore, the system can also improve the yield rate by 0.18% or 12.4% while suffering 0.38% or 1.7% of accuracy loss, respectively.

Through silicon via (TSV) is considered as the near-future solution to realize low-power and high-performance 3D-integrated circuits (3D-ICs) and 3D-Network-on-Chips (3D-NoCs). However, the lifetime reliability issue of TSV due to its fault sensitivity and the high operating temperature of 3D-ICs, which also accelerates the fault rate, is one of the most critical challenges. Meanwhile, most current works focus on detecting and correcting TSV defects after manufacturing without considering high-temperature nodes’ impact on lifetime reliability. Besides, the recovery for defective clusters is also challenging because of costly redundancies. In this work, we presentHotCluster: a hotspot-aware self-correction platform for clustering defects in 3D-NoCs to help understand and tackle this problem. We first give a method to predict normalized fault rates and place redundant TSV groups according to each region’s fault rate. In our particular medium fault rate (normalized to the coolest area),HotClusterreduces about 60% of the redundancies in comparison to the uniformly distributed redundancies while having a higher ratio of router working in a normal state. Furthermore,HotClusterintegrates both online (weight based) and offline (max-flow min-cut offline method) mapping algorithms to help the system correct the faulty TSV clusters. The experimental results show that both the max-flow min-cut offline method and weight-based online mode with a redundancy of 0.25 exhibits less than 1% of routers disabled under 50% defect rates.

In order to detect and localize through-silicon-via (TSV) failures in both manufacturing and operating phases, most of the existing methods use a dedicated testing mechanism with long response time and prerequisite interruptions for online testing. This article presents an error correction code (ECC)-based method named “TSV on-communication test” (TSV-OCT) to detect and localize faults without halting the operation of TSV-based 3-D-IC systems. We first propose a statistical detector, a method to detect open and short defects in TSVs that work in parallel with data transactions. Second, we propose an isolation-and-check algorithm to enhance the localization ability of the method. Moreover, the Monte Carlo simulations show that the proposed statistical detector increases ×2 the number of detected faults when compared to conventional ECC-based techniques. With the help of isolation and check, TSV-OCT localizes the number of defects up to ×4 and ×5 higher. In addition, the response time is kept below 65000 cycles, which could be easily integrated into real-time applications. On the other hand, an implementation of TSV-OCT on a 3-D Network-on-Chip (NoC) router shows no performance degradation for testing while having a reasonable area overhead.

Flow-in-Cloud(FiC) is an acceleration platform designed to make a virtual monolithic large FPGA image from a number of mid-range economical FPGAs. We will show the live demonstration of the acceleration example of FiC with 24 boards through the network.

FiC (Flow-in-Cloud) is a multi-FPGA system to achieve monolithic large scale FPGA with across multiple FPGAs for computational-heavy applications. The FiC system employs multiple economical mid-range FPGAs and connect them directly with flexible and high bandwidth interconnection network. We developed FiCSW board as a 1st generation of FPGA board in the FiC project. The FiCSW design, since the FPGA is used as both computational resource and the network circuit switch, there are no host server for FPGA needed like other server-based multi FPGA architecture. This design strategy helps scalable FPGA fabric in low-cost. However, from the system manageability's perspective, the strategy is hard to handle multiple FPGA nodes without management system. In this paper, we mainly focused on the management system on the FiCSW multi-FPGA system, introducing the system architecture and implementation, and working application on the FiCSW prototype system.

Various parallel applications, such as numerical convergent computation and multimedia processing, have intrinsic tolerance to inaccuracies that allow soft errors, i.e. bit flips, on a chip. However, existing Network-on-Chips (NoCs) guarantee error-free data transfer; thus, encountering limits to reduce the power consumption. In this context, we propose an approximate dual-voltage NoC, called AxNoC. An AxNoC router uses a per-flit look-ahead power management so that headers and important-data flits are perfectly transferred at a high voltage while the remaining flits may incur bit flips by decreasing the supply voltage. An AxNoC router isolates the critical path when the supply voltage is low since such a critical path is enabled only at high voltage. The critical path isolation enables low-voltage operation to work at the same operating frequency at high voltage. An AxNoC router was implemented using a 28nm process and the evaluation results illustrate its efficiency to reduce the power consumption reaching up to 43% while incurring a small area overhead that does not exceed 6.2%. We also demonstrate that AxNoC exhibits an acceptable accuracy illustrated in a sufficiently small geomean of error.

The component's failure in network-on-chips (NoCs) has been a critical factor on the system's reliability. In order to alleviate the impact of faults, fault tolerance has been investigated in the recent years to enhance NoC's robustness. Due to the vast selection of fault-tolerance mechanisms and critical design constraints, selecting and configuring an appropriate mechanism to satisfy the fault-tolerance requirements constitute new challenges for designers. Consequently, reliability assessment has become prominent for the early stages of manufacturing process to solve these problems. This paper approaches the fault-tolerance analysis by providing an analytical model to approximate the lifetime reliability and compares it with a system-level simulation. Based on the proposed approach, we measure the fault-tolerance efficiency using a new parameter, named reliability acceleration factor. The goal of this paper is to provide an efficient and accurate reliability assessment to help designers easily understand and evaluate the advantages and drawbacks of their potential fault-tolerance methods.

Optical Network-on-Chip is a solution to for power and throughput bottlenecks of current technology. The higher bandwidth is achieved by the light speed transmissions, and the power required to transmit data in the optical domain is much lower. This is a disruptive technology solution to problems arising from silicon-based computing. In this paper, we present a fault-tolerant optical router (FTTDOR) with its electrical control module towards the design of a highly-reliable low-power three dimensional Networks-on-Chip (PHENIC). FTTDOR uses redundancy only in critical locations, to assure accuracy of the packet transmission even after a faulty ring resonator appears. The proposed optical router is decomposed non-blocking, with minimal ring resonators, and requires no resonators for straight travel (East to West, North to South, and Up to Down, as well as their inverses). Simulation results show that the network can maintain a 98% throughput after 3% faults, and 89% after 20% faults. These results come with a reduction of micro-ring resonators to 65% of the amount present in a conventional crossbar router. Simulation of the electrical control module and router show that it has a total area of around 20,000 μm2and consumes 3.8mW at 600MHz.

One of the major design challenges of Network-on-Chip interconnect is the storage buffers. They occupy a significant portion of the system's area and so they are considered as main "power-hungry" components. Deciding the appropriate buffers size and implementation in these systems is the key technique for increasing system performance and also for reducing overall area and power consumption. However, this goal is very hard to achieve with traditional design approaches, where design decisions of the main architectural parameters are generally made with slow and inaccurate software simulation or theoretical modeling. In order to quickly capture and decide the optimal buffers size and the whole system behavior, we propose in this work an efficient design method for Network-on-Chip architecture based on a novel run-time monitoring mechanism (RMM). The system monitors the traffic flow at different system's resources and sends the monitored run-time traffic information to a specialized controller. In addition, our proposed design method allows to easily compute optimal architecture hardware parameters (i.e Buffer size) and allocate the appropriate values on demand to satisfy the requirements of any given application. The RMM mechanism was designed in hardware and integrated into our NoC system (PNoC). From the evaluation results, we conclude that the system performance in terms of execution time was about 27% better when compared with traditional design methods over several benchmark programs.