With VLSI circuit feature size scaling down, it is becoming more difficult and expensive to achieve a desired level of yield. Error-tolerance employs defective chips that occasionally produce erroneous yet acceptable results in targeted applications, and has been proposed as one way to increase effective yield. These chips are characterized by criteria set by specific applications. Error rate, an upper-bound on how frequent errors occur at an output, is one such criterion. In this article we focus on the following problem: given a combinational logic circuit that is defective, and hence occasionally produces an erroneous output, how can we determine the error rate of each output line by using ones counting? The results of this work can also be used for runtime error estimation in aging systems and in environments where soft-errors are produced.

As CMOS scaling continues to decrease and new technologies emerge, feature sizes approach molecular sizes. Due to high defect rates, process variations and quantum effects, manufacturing yields have decreased. To increase the effective yield, error-tolerance, which allows for some defective chips to be employed in systems that can tolerate errors, has been proposed. To support error-tolerance, the acceptability of defective chips must be quantified according to certain measures. A new measure is proposed in this paper, namely significance-based error-rate (SBER). SBER combines two previously studied error-tolerance measures, namely error-significance and error-rate. In this paper we introduce three different ways to quantify the SBER value(s) of a defective chip using built-in self-test (BIST). These techniques cover the following scenarios: (1) multiple copies of a target circuit where at least one copy is non-defective; (2) multiple copies of a target circuit where none are defect free; and (3) single copy of a defective target circuit. For each scenario, the statistical characteristics of the estimation of the SBER value are discussed.

As feature size approaches molecular dimensions and the number of devices per chip reaches astronomical values, VLSI manufacturing yield significantly decreases. This motivates interests in new computing models. One such model is called error tolerance. Classically, during the postmanufacturing test process, chips are classified as being bad (defective) or good. The main premise in error-tolerant computing is that some bad chips that fail classical go/no-go tests and do indeed occasionally produce erroneous results actually provide acceptable performance in some applications. Thus, new test techniques are needed to classify bad chips according to categories based upon their degree, of acceptability with respect to predetermined applications. One classification criterion is error rate. In this paper, we first describe a simple test structure that is a minor extension to current scan-test and built-in self-test structures and that can be used to estimate the error rate of a circuit. We then address three theoretical issues. First, we develop an elegant mathematical model that describes the key parameters associated with this test process and incorporates bounds on the error in estimating error rate and the level of confidence in this estimate. Next, we present an efficient testing procedure for estimating the error rate of a circuit under test. Finally, we address the problem of assigning bad chips to bins based on their error rate. We show that this can be done in an efficient, hence cost-effective, way and discuss the quality of our results in terms of such concepts as increase effective yield, yield loss, and test escape