In this paper, a novel pixel architecture with logarithmic and linear multi-mode distance calculation, is presented using a single photon avalanche diode (SPAD) for light detection and ranging (LiDAR) applications. The pixel gives an initial logarithmic response using a current starved pseudo-analog design, eventually switching to a linear response using a separate circuit with a highly stable current source. The logarithmic response is used to obtain a better resolution (post digitisation) for the smaller distances. While, the linear mode is configured for longer distances. Combination of the two modes results in a larger full scale range (FSR) with better resolution throughout the range. This approach reduces an unwanted high data-rate and requirement for a high resolution analog-to-digital converter (ADC). The proposed pixel is designed in standard CMOS 65 nm technology from TSMC. The pixel has a minimum detection distance of 2.34 cm (199.5 ps), a logarithmic depth resolution of 2.34 cm - 0.308 m and a linear depth resolution 0.59 m (3.9 ns). The dynamic range of the pixel is 500 m. The maximum voltage error of the logarithmic part is -1.86% to +0.5%.

We present an ultra-low-power band-gap reference-based regulator and a unique method of generating a proportional-to-absolute-temperature (PTAT) voltage and a PTAT current. The PTAT current is used to generate a BJT complementary-to-absolute-temperature (CTAT) voltage. This CTAT voltage and PTAT voltage are added to generate a regulated output voltage in the negative feedback loop to drive the load. The output of the proposed regulator is temperature stable from −20° C to 85° C with a mean variation of less than 20 ppm/° C. The proposed technique eliminates the need for an additional start-up circuitry, which is mandatory for conventional architectures. The 1.18 V output voltage regulator, designed in a 180-nm CMOS process, has a simulated line regulation of 0.1 %/V with a power consumption of 15 nW at room temperature. The proposed regulator can drive the load from 0 to 30 mA.

In this work, a novel low-noise active pixel sensor (APS) is proposed which deploys in-pixel chopping and switched biasing to reduce the temporal noise. The source follower (SF) of an APS is the major contributor of the temporal noise. The proposed sensor is a modified conventional 3T pixel with an nwell/psub photodiode (PD) as photo-sensing element. To implement in-pixel chopping, two minimal sized additional nMOS switches are used per pixel. The switched biasing is implemented using two column-level (ps and ns) switches without affecting the pixel fill-factor (FF). The noise reduction techniques are validated through measured results obtained from a prototype sensor fabricated in 350 nm OPTO process from AMS. The sensor consists of a 2-D array of$128\times 128$pixels. The proposed pixel is designed with an area of$11\mu \mathrm{m}\times 11\mu \mathrm{m}$achieving a FF of 35%. A total noise reduction (and enhancement in dynamic range (DR)) of around 16 dB is achieved from in-pixel chopping with 8 MHz chopping frequency$(f_{\text{ch}})$and switched biasing.

In this paper, a time-of-flight 3-D camera is presented for indoor/outdoor high-speed applications. A three-phase algorithm is proposed using one-tap/capacitor in-pixel background light subtraction. By integrating the background light only once, the standard four-phase time-of-flight operation is done in three-phases. The use of a single tap in the proposed pixel provides background light subtraction with lower mismatch and additionally, increases the camera speed. A 24 × 24 pixel array image sensor, fabricated in AMS 0.35-μm CMOS process is characterized in 2-D and 3-D mode for background light subtraction and distance estimation. The pixel pitch is 48 μm with 17.36% fill-factor. The sensor subtracts 125-klx background light with 8.2-cm distance offset at 80-cm object distance, without using an optical filter. The background-to-signal-ratio is 32.04 dB while frame rate of the camera is 207 and 100 fps in 2-D and 3-D mode, respectively.