This paper describes the MetaCore system which is an application-specific instruction-set processor (ASIP) development system targeted for digital signal processor (DSP) applications. The goal of the MetaCore system is to offer an efficient design methodology meeting specifications given as a combination of performance, cost, and design turnaround time. The MetaCore system consists of two major design stages: design exploration and design generation. In the design exploration stage, MetaCore system accepts a set of benchmark programs and structural/behavioral specifications for the target processor and estimates the hardware cost and performance for each hardware configuration being explored. Once a hardware configuration and instruction set are chosen, the system helps generate the target processor design in the form of hardware description language (HDL) along with the application program development tools such as C compiler, assembler, and instruction set simulator. The effectiveness of the MetaCore system was verified with a successful design of MDSP-II, a programmable DSP processor targeted for mobile communication.

We propose a new technique called node sampling to speed up the probability-based power estimation methods. It samples and processes only a small portion of total nodes to estimate the power consumption of a circuit. It is different from the previous speed-up techniques for probability-based methods in that the previous techniques reduce the processing time for each node while our method reduces the number of nodes actually processed. In addition, it is also different from the previous statistical sampling simulation techniques for simulation-based methods in that the previous methods sample the input vectors while our method samples the nodes in the network. The experimental results are very encouraging. The proposed method shows on the average more than 80% and 60% reductions of simulation run time under 20% and 5% error bounds, respectively.

Application specific instructions play an important role in reducing the required code size and increasing performance in embedded DSP systems. This paper describes a new approach to generate application specific instructions for DSP applications. The proposed approach is based on a modified subset-sum problem and supports multicycle complex instructions, as well as single-cycle instructions, while the previous state-of-the-art approaches generate only the single-cycle instructions or just select instructions from the fixed super-set of possible instructions. In addition, the proposed approach can also be applied to the case that instructions are predefined. Experimental results on real applications show that Various given constraints can be met by the generated set of application specific instructions without attaching special hardware accelerators.

This paper describes the MetaCore system which is an ASIP (Application-Specific Instruction set Processor) development system targeted for DSP applications. The goal of MetaCore system is to offer an efficient design methodology meeting specifications given as a combination of performance, cost and design turnaround time.

In this paper, we present an approach to synthesize multiple behavior modules. Given n DFGs to be implemented the previous methods scheduled each of them sequentially, and implemented them as a single module. Though the method Is appropriate for sharing the functional units, it ignored the following two aspects: (1) different interconnection patterns among DFGs can increase the interconnection area and delay of the critical path, (2) the sequential scheduling of DFGs has a difficulty in considering the effects on the other DFGs not scheduled yet. We show an efficient way to solve the problems using a selective grouping method and the extensions of the traditional scheduling methods. The experimentation reveals that the result obtained by the proposed method is better to reduce interconnection area and to meet the timing constraints than those obtained by the previous methods.

Article Free Access Share on Synthesis of application specific instructions for embedded DSP software Authors: Hoon Choi Department of Electrical Engineering, Korea Advanced Institute of Science and Technology, Taejon, Korea Department of Electrical Engineering, Korea Advanced Institute of Science and Technology, Taejon, KoreaView Profile , Seung Ho Hwang Department of Electrical Engineering, Korea Advanced Institute of Science and Technology, Taejon, Korea Department of Electrical Engineering, Korea Advanced Institute of Science and Technology, Taejon, KoreaView Profile , Chong-Min Kyung Department of Electrical Engineering, Korea Advanced Institute of Science and Technology, Taejon, Korea Department of Electrical Engineering, Korea Advanced Institute of Science and Technology, Taejon, KoreaView Profile , In-Cheol Park Department of Electrical Engineering, Korea Advanced Institute of Science and Technology, Taejon, Korea Department of Electrical Engineering, Korea Advanced Institute of Science and Technology, Taejon, KoreaView Profile Authors Info & Claims ICCAD '98: Proceedings of the 1998 IEEE/ACM international conference on Computer-aided designNovember 1998 Pages 665–671https://doi.org/10.1145/288548.289109Published:01 November 1998Publication History 18citation223DownloadsMetricsTotal Citations18Total Downloads223Last 12 Months16Last 6 weeks2 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF

The possible overestimation of timing analysis under the floating mode has been known for more than five years. However the transition mode that can resolve the problem has not been widely employed in real designs due to the following reasons: (1) the source of the overestimation of the floating delay has not been thoroughly analyzed, (2) the previous transition delay computing method based on the symbolic simulation is not as efficient as that for the floating delay, and (3) the importance of the transition delay has not been sufficiently demonstrated by experiments. In this paper, we first present a thorough and formal analysis on the reasons of the overestimation of the floating delay including ones caused by the spatio-temporal correlation among the primary input signals. Based on the analysis, we present a new practical sensitization criterion for the transition mode. Experimental results validating our work are also included.

We propose a new method to improve the accuracy of the transition density for the estimation of delay dependent switching activities in combinational circuits. In the previous method, glitching sensitivity concept was defined and used to modify the transition density so as to generate and propagate the glitch. To account for the inertial delay effect, the same technique that is commonly used in logic simulators to filter out unacceptably short pulses was used. However, since it does not keep transition density at each occurrence time separately, it is not adequate for the accurate estimation of glitch and inertial delay effect. In addition, it underestimates the difference between probabilistic property of the transition density and the deterministic property of signals in logic simulations in computing inertial delay effect. We describe the problems of the previous methods and propose a new method called time-stamped transition density to solve the problems. We also show the extensions of the method to consider possible delay variation due to imperfections in the manufacturing process. The experimental results demonstrate the validity of our proposed method.

The correctness-checking problem of a finite-state machine is considered. The concept of machine cover is revived and used as the basis of the formulation of the verification problem of the design correctness of finite-state machines. The concept of machine cover enables the verifier to efficiently check the sufficiency. The verifier checks to see if the implementation is correct with respect to its specification, which is given as a form of finite-state machine. Since in general the state encoding information is not available for verification purposes, it is assumed that the encoding information is missing. An efficient algorithm for the verification problem is presented along with its implementation. Experimental results show that the approach is promising in terms of speed.>

Electrical-logic (ELogic) is a form of circuit modeling and simulation that solves for the amount of time required for a network variable to make a particular change, rather than solving for the network variables at the given time point as in conventional circuit simulation. Three ELogic algorithms are presented. The algorithms are based on the nodal analysis method and provide a continuous speed-precision tradeoff between the circuit level and logic/switch level, as well as providing more accurate timing information than existing strength-oriented logic simulation or switch-level simulation at comparable speed. These ELogic algorithms have been used to implement both a simulator, ELOSIM, and a timing verifier, E-Crystal, and experimental results from these programs are also included.>

A new delay modeling technique for accurate timing verification of digital MOS circuits is presented. The technique is based on the ELogic approach and provides the user with a continuous speed-accuracy trade-off in addition to more accurate timing information than available with existing switch-level timing verifiers. The new technique has been implemented in the Crystal timing analyzer and experimental results comparing this method with those used in Crystal are included. Comparisons indicate that the ELogic-based approach, while slower than present approaches, provides a more robust and more accurate delay analysis at the switch level.