Homomorphic Encryption (HE) enables computations to be performed directly on encrypted data, providing strong cryptographic security guarantees and preserving data confidentiality in untrusted environments such as cloud computing, high-performance computing, and machine learning platforms. Among existing HE schemes, Cheon-Kim-Kim-Song (CKKS) enables efficient approximate arithmetic over encrypted real-valued data, making it particularly well suited for numerical workloads. However, its practical deployment remains constrained by the substantial computational cost of its core ciphertext operations. In this work, we present a software-based acceleration of CKKS arithmetic kernels on ARM Neoverse processors through Single Instruction, Multiple Data (SIMD) vectorization using the Scalable Vector Extension (SVE). Our approach targets the widely adopted Microsoft SEAL library and introduces SVE-optimized implementations of the key polynomial-arithmetic primitives underlying CKKS ciphertext addition, multiplication, and rotation. By leveraging data-level parallelism, vector-length-agnostic programming, and microarchitectural features of the target processor, the proposed optimizations enhance execution efficiency while preserving functional correctness and compatibility with the existing library interface. Experimental evaluation on an ARM Neoverse V2 platform (NVIDIA Grace processor) demonstrates performance improvements of 8-14% for ciphertext multiplication and rotation, and approximately 30% for addition, across multiple CKKS parameter configurations. These results highlight the potential for more efficient processor-only execution of homomorphic encryption workloads through architecture-aware optimization.

This paper presents a performant and compact hardware accelerator for the ML-KEM algorithm, compliant with the NIST FIPS 203 specification and implemented in a 22nm ASIC technology. The proposed design supports all three standardized security levels (ML-KEM-512, -768, and -1024) using a unified, parameter-agnostic architecture that avoids logic duplication. The design relies exclusively on SRAM blocks for storage, completely eliminating FIFOs and intermediate buffers, while flip-flops are used only in timing-critical paths to achieve high-frequency operation with minimal area overhead. Among all known ASIC implementations, our architecture achieves the best normalized area-time product across all ML-KEM parameter sets, demonstrating efficiency and scalability, while also delivering the lowest power and energy per operation among state-of-the-art solutions. These results make the proposed design a strong candidate for real-world post-quantum cryptographic deployments on constrained hardware and IoT platforms.

The European Union’s efforts towards technological sovereignty in High-Performance Computing are driving research and development of RISC-V-based supercomputers. The DARE SGA1 project, in particular, aims to develop chips designed and owned by Europeans. This paper introduces the Italian contribution to DARE SGA1 regarding pathfinding activities toward future RISC-V-based accelerator designs, reliability improvements, system software, and AI and Quantum Chemistry applications.

As an essential technology for spectrum sensing and dynamic spectrum access, automatic modulation classification (AMC) is a critical step in intelligent wireless communication systems, aiming at automatically recognizing the modulation schemes of received signals. In practice, AMC is challenging due to the influence of communication environment and signal parameters, such as unknown channels, noise, symbol rate, signal length, and sampling frequency. In this survey, we investigated a series of typical AMC methods, including key technology, performance comparisons, advantages, challenges, and future key development directions. According to the methodology and processing flow, AMC methods are divided into three categories: likelihood‐based (Lb) methods, feature‐based (Fb) methods, and deep learning methods. The technical details of various types of methods are introduced and discussed, such as likelihood distributions, artificial features, classifiers, and network structures. Then, extensive experimental results of state‐of‐the‐art AMC methods on public or simulated datasets are compared and analyzed. Despite the achievements that have been made, there are still limitations of the individual methods, including generalization capability, reasoning efficiency, model complexity, and robustness. In the end, we summarized the severe challenges faced by AMC and key future research directions.

This work describes the hardware implementation of a cryptographic accelerators suite, named Crypto-Tile, in the framework of the European Processor Initiative (EPI) project. The EPI project traced the roadmap to develop the first family of low-power processors with the design fully made in Europe, for Big Data, supercomputers and automotive. Each of the coprocessors of Crypto-Tile is dedicated to a specific family of cryptographic algorithms, offering functions for symmetric and public-key cryptography, computation of digests, generation of random numbers, and Post-Quantum cryptography. The performances of each coprocessor outperform other available solutions, offering innovative hardware-native services, such as key management, clock randomisation and access privilege mechanisms. The system has been synthesised on a 7 nm standard-cell technology, being the first Cryptoprocessor to be characterised in such an advanced silicon technology. The post-synthesis netlist has been employed to assess the resistance of Crypto-Tile to power analysis side-channel attacks. Finally, a demoboard has been implemented, integrating a RISC-V softcore processor and the Crypto-Tile module, and drivers for hardware abstraction layer, bare-metal applications and drivers for Linux kernel in C language have been developed. Finally, we exploited them to compare in terms of execution speed the hardware-accelerated algorithms against software-only solutions.

The TEXTAROSSA project aims to bridge the technology gaps that exascale computing systems will face in the near future in order to overcome their performance and energy efficiency challenges. This project provides solutions for improved energy efficiency and thermal control, seamless integration of heterogeneous accelerators in HPC multi-node platforms, and new arithmetic methods. Challenges are tacked through a co-design approach to heterogeneous HPC solutions, supported by the integration and extension of HW and SW IPs, programming models, and tools derived from European research.

The complexity of vehicle applications and the need of reducing the number of processing units are giving great audience to system virtualization. Virtualized architectures with diverse Automotive Safety Integrity Level (ASIL) in the same multicore hardware, known as Mixed Criticality Systems (MCSs), offer flexibility but are extremely challenging in terms of timing validation and resources partitioning. At the same time, RISC- V technologies are becoming central in automotive thanks to open source licensing and customizable solutions. However, most of these architectures cannot sustain MCSs for the absence of features that can be performed only through hardware extensions. In this paper we define details and show a preliminary design and synthesis of a Programmable PMU (PPMU). In virtual systems an extension reporting hardware performance is essential to absolve timing analysis and shared resources balancing purposes. Moreover, in the paper we present a table containing major Hardware Events (HEs) we are interested in, and that can be monitored. The HEs are classified by the role they have in a MCS: Functional Safety (FuSa) analysis or Performance analysis. The synthesis of the PPMU highlighted that the device introduces a limited hardware overhead, e.g. in the worst case the unit uses less than 3 % of available programmable logic of a xczu9eg FPGA device.

This paper presents the design and the experimental characterization of a 10 Gb/s electronic driver for silicon Mach-Zehnder modulators (MZMs). This driver is able to operate in harsh environments characterized by radiation levels up to 1 Grad(SiO2) total ionizing dose (TID). To compensate for the detrimental effects that radiation produces on the target 65 nm bulk silicon technology both device- and circuit-level radiation hardened by design (RHBD) techniques are developed and implemented. Extreme TID levels are faced using long-channel transistors with enclosed layout, avoiding the use of p-MOSFETs, and implementing a differential self-biased cascode architecture with common-mode feedback. Band-widening techniques, e.g., inductive peaking, cross-coupled capacitors, and buffer chaining, have been used to improve the driver’s frequency response and reach the targeted data rate. Electrical measurements show 10 Gb/s waveforms with an eye diagram amplitude suitable for MZM driving. Electro-optical measurements performed connecting the electronic driver to a silicon photonic MZM confirm the achievement of a 10 Gb/s system-level operability. The radiation hardness of the driver is verified by exposing the integrated circuit to X-rays. The measurements confirm the ability of the driver to work up to 1 Grad with an eye amplitude reduction of only 10% and a 7% increment in the rise and fall times, validating the effectiveness of the implemented RHBD techniques.

This article presents a cryptographic hardware (HW) accelerator supporting multiple advanced encryption standard (AES)-based block cipher modes, including the more advanced cipher-based MAC (CMAC), counter with CBC-MAC (CCM), Galois counter mode (GCM), and XOR-encrypt-XOR-based tweaked-codebook mode with ciphertext stealing (XTS) modes. The proposed design implements advanced and innovative features in HW, such as AES key secure management, on-chip clock randomization, and access privilege mechanisms. The system has been tested in a RISC-V-based system-on-chip (SoC), specifically designed for this purpose, on an Ultrascale + Xilinx FPGA, analyzing resource and power consumption, together with system performances. The cryptoprocessor has been then synthesized on a 7-nm CMOS standard-cells technology; performances, complexity, and power consumption information are analyzed and compared with the state of the art. The proposed cryptoprocessor is ready to be embedded within the innovative European Processor Initiative (EPI) chip.

High-Performance Computing (HPC) is one of the strategic priorities for research and innovation worldwide due to its relevance for industrial and scientific applications. We envision HPC as composed of three pillars: infrastructures, applications, and key technologies and tools. While infrastructures are by construction centralized in large-scale HPC centers, and applications are generally within the purview of domain-specific organizations, key technologies fall in an intermediate case where coordination is needed, but design and development are often decentralized. A large group of Italian researchers has started a dedicated laboratory within the National Interuniversity Consortium for Informatics (CINI) to address this challenge. The laboratory, albeit young, has managed to succeed in its first attempts to propose a coordinated approach to HPC research within the EuroHPC Joint Undertaking, participating in the calls 2019--20 to five successful proposals for an aggregate total cost of 95M€. In this paper, we outline the working group's scope and goals and provide an overview of the five funded projects, which become fully operational in March 2021, and cover a selection of key technologies provided by the working group partners, highlighting their usage development within the projects.

To achieve high performance and high energy efficiency on near-future exascale computing systems, three key technology gaps needs to be bridged. These gaps include: energy efficiency and thermal control; extreme computation efficiency via HW acceleration and new arithmetics; methods and tools for seamless integration of reconfigurable accelerators in heterogeneous HPC multi-node platforms. TEXTAROSSA aims at tackling this gap through a co-design approach to heterogeneous HPC solutions, supported by the integration and extension of HW and SW IPs, programming models and tools derived from European research.

The functionality advancements and novel customer features that are currently found in modern automotive systems require high-bandwidth and low-latency in-vehicle communications, which become even more compelling for autonomous vehicles. In a recent effort to meet these requirements, the IEEE Time-Sensitive Networking (TSN) task group has developed a set of standards that introduce novel features in Switched Ethernet. TSN standards offer, for example, a common notion of time through accurate and reliable clock synchronization, delay bounds for real-time traffic, time-driven transmissions, improved reliability, and much more. In order to fully utilize the potential of these novel protocols in the automotive domain, TSN should be seamlessly integrated into the state-of-the-art and state-of-practice model-based development processes for automotive embedded systems. Some of the core phases in these processes include software architecture modeling, timing predictability verification, simulation, and hardware realization and deployment. Moreover, throughout the development of automotive embedded systems, the safety and security requirements specified on these systems need to be duly taken into account. In this context, this work provides an overview of TSN in automotive applications and discusses the recent technological developments relevant to the adoption of TSN in automotive embedded systems. The work also points at the open challenges and future research directions.

Abstract With the arrival of the open-source RISC-V processor architecture, there is the chance to rethink Deep Neural Networks (DNNs) and information representation and processing. In this work, we will exploit the following ideas: i) reduce the number of bits needed to represent the weights of the DNNs using our recent findings and implementation of the posit number system, ii) exploit RISC-V vectorization as much as possible to speed up the format encoding/decoding, the evaluation of activations functions (using only arithmetic and logic operations, exploiting approximated formulas) and the computation of core DNNs matrix-vector operations. The comparison with the well-established architecture ARM Scalable Vector Extension is natural and challenging due to its closedness and mature nature. The results show how it is possible to vectorize posit operations on RISC-V, gaining a substantial speed-up on all the operations involved. Furthermore, the experimental outcomes highlight how the new architecture can catch up, in terms of performance, with the more mature ARM architecture. Towards this end, the present study is important because it anticipates the results that we expect to achieve when we will have an open RISC-V hardware co-processor capable to operate natively with posits.

Nowadays, real-time applications are exploiting DNNs more and more for computer vision and image recognition tasks. Such kind of applications are posing strict constraints in terms of both fast and efficient information representation and processing. New formats for representing real numbers have been proposed and among them the Posit format appears to be very promising, providing means to implement fast approximated version of widely used activation functions in DNNs. Moreover, information processing performance are continuously improved thanks to advanced vectorized SIMD (single-instruction multiple-data) processor architectures and instructions like ARM SVE (Scalable Vector Extension). This paper explores both approaches (Posit-based implementation of activation functions and vectorized SIMD processor architectures) to obtain faster DNNs. The two proposed techniques are able to speed up both DNN training and inference steps.

This work presents a video-camera-based fire/smoke sensing technique for early warning in antifire surveillance systems. By exploiting R-CNN (Region Convolutional Neural Network), a detection technique is developed for the measurement of the smoke and fire characteristics in restricted video surveillance environments, both indoor (e.g. a railway carriage, container, bus wagon, homes, offices), or outdoor (e.g. storage or parking areas). The considered application scenario, to reduce costs, is composed of a single, fixed camera per scene, working in the visible spectral range already installed in a closed-circuit television system for surveillance purposes. The training phase is done with indoor and outdoor image sets, with both smoke and non-smoke scenarios to assess the capability of true-positive/true-negative detection and false-positive/false-negative rejection. To generate the training set, a Ground Truth Labeler app is used and applied to the open-access Firesense dataset, including tens of indoor and outdoor fire/ smoke scenes developed as the output of an FP7 project, plus other videos not publicly available, provided by Trenitalia during specific fire/smoke tests on railway wagons performed at their testing facility in Osmannoro, Italy. The achieved results show that the proposed R-CNN technique is suitable for the creation of a smart video-surveillance system for fire/smoke detection.

Modern cars consist of a number of complex embedded and networked systems with steadily increasing requirements in terms of processing and communication resources. Novel automotive applications, such as automated driving, rise new needs and novel design challenges that cover a broad range of hardware/software engineering aspects. In this context, this paper provides an overview of the current technological challenges in on-board and networked automotive systems. This paper encompasses both the state-of-the-art design strategies and the upcoming hardware/software solutions for the next generation of automotive systems, with a special focus on embedded and networked technologies. In particular, this paper surveys current solutions and future trends on models and languages for automotive software development, on-board computational platforms, in-car network architectures and communication protocols, and novel design strategies for cybersecurity and functional safety.

The papers in this special section focus on embedded and networked systems for intelligent vehicles and robots. Embedded and networked systems for intelligent vehicles and robots are expected to have a significant economic, societal, and technological impact on industrial and automotive applications. Among the aspects that will benefit from these technologies the first one is safety, thanks to the reduction of accidents caused by human errors. Another positive effect is expected on sustainability, thanks to the increase in transport systems efficiency. Comfort and inclusiveness will be also improved, ensuring users’ freedom for other activities and “mobility for all.” Logistics and factory automation are among the main areas that will take advantages from intelligent vehicles and robots, that are expected to play a key role in Industry 4.0 scenarios, the so-called fourth industrial revolution, where intelligent vehicles and industrial robots will move and operate autonomously and cooperatively. Such a revolution has many key enabling technologies, such as, networked sensors, actuators, and embedded computing and control platforms, that will be distributed on-board the vehicle/robot. The contribution of artificial intelligence and deep learning computing platforms is also emerging to achieve full intelligent autonomous mobility of vehicles and robots.

This paper presents the integrated circuit design, targeting a CMOS 65 nm 1.2 V technology, of a high-speed driver that provides the differential input signals to a Mach Zender Modulator (MZM), and allows tuning of the MZM operating point through adjustment of the bias voltage. A multi-voltage domain circuit is proposed, where each domain is isolated through deep n-well trenches, to face the high voltage swing and the bias regulation requirements of the MZM. The MZM device, whose prototype has been implemented in silicon photonics iSiPP50G technology, is emerging as a promising solution for radiation tolerant, several hundreds of Mrad, and high-speed, in the range of 10 Gbps, optical links. These stringent requirements are needed in high energy physics experiments in the upgrade of the Large Hadron Collider or in future Linear Colliders.

This work explores the potentiality of millimeter waves (mmW) as physical layer in industrial wireless networks. Innovative models and a link design method are proposed to achieve reliable communication, at a distance of tens of meters for a single hop, even in harsh environments. By exploiting the worldwide-free band of several GHz, available around 60 GHz, mmW links allow to achieve a performance boosting of up to two orders of magnitude, w.r.t. conventional sub-6-GHz wireless links, in indoor industrial environments. Time slotted channel hopping and frequency-diversity can be implemented with a large number of channels, and with high bit rate (several Mb/s per channel). This allows for robust networking of high data-rate sensors, such as cameras, radars, or laser scanners. Featuring a low bit error rate, mmW communication allows for low-latency link and large number of hops in networks with a large radius. Finally, it ensures interference separation from operating frequencies of electrical machines, switching converters, and other industrial wireless networks (e.g., 802.11 or 802.15). Implementation results for key HW blocks in low-cost technologies show the feasibility of mmW communication nodes with low-power and compact size.

This work proposes models and a link design method to exploit the potentiality of millimeter waves (mmW) as physical layer of industrial networking protocols. This work shows that, even taking into account harsh operating conditions, a transmitted power of 10 dBm allows for reliable connections at a distance of tens of meters. With respect to traditional sub-3 GHz wireless connections used in indoor industrial environments, mmW links feature worldwide-unlicensed ISM (Industrial Scientific Medical) wideband. This can be exploited to implement frequency-hopping and frequency-diversity techniques to increase link robustness. Operating at mmW allows for inherent interference separation from operating frequencies of electrical machine, power switching converters and other wireless connections. Implementation results of key hardware building blocks with CMOS and PCB technologies prove the feasibility of mmW nodes with low-power and low size.

This paper presents the design and the characterization in nanoscale CMOS technology of a Network Interface (NI) for on-chip communication infrastructure with hardware support of advanced networking functionalities: store & forward (S&F) transmission, error management, power management, ordering handling, security, QoS management, programmability, end-to-end protocol interoperability, remapping. The design has been conceived as a scalable architecture: The advanced features can be added on top of a basic NI core implementing data packetization and conversion of protocols, frequency and data size between the connected Intellectual Property (IP) core and the on chip network. The NI can be configured to reach the desired tradeoff between supported services and circuit complexity.

The battery is a fundamental component of electric vehicles, which represent a step forward towards sustainable mobility. Lithium chemistry is now acknowledged as the technology of choice for energy storage in electric vehicles. However, several research points are still open. They include the best choice of the cell materials and the development of electronic circuits and algorithms for a more effective battery utilization. This paper initially reviews the most interesting modeling approaches for predicting the battery performance and discusses the demanding requirements and standards that apply to ICs and systems for battery management. Then, a general and flexible architecture for battery management implementation and the main techniques for state-of-charge estimation and charge balancing are reported. Finally, we describe the design and implementation of an innovative BMS, which incorporates an almost fully-integrated active charge equalizer.

The design and the implementation of a flexible and cost-effective embedded system for real-time correction of fish-eye automotive cameras is presented. Nowadays many car manufacturers already introduced on-board video systems, equipped with fish-eye lens, to provide the driver a better view of the so-called blind zones. A fish-eye lens achieves a larger field of view (FOV) but, on the other hand, causes distortion, both radial and tangential, of the images projected on the image sensor. Since radial distortion is noticeable and dangerous, a real-time system for its correction is presented, whose low-power, low-cost and flexibility features are suitable for automotive applications.

The flexibility of an Intelligent Power Switch (IPS) designed in HV-CMOS technology for incandescent lamp in automotive scenarios has been evaluated for the driving of a LED in presence of wiring parasitics. The paper presents how it is possible, through proper reconfiguration of the flexible IPS, to reduce the undesired ringing phenomenon when driving a LED with wiring parasitics thus reducing Electromagnetic Interferences (EMI) and spikes on supply voltage. Electrical simulation and experimental measurements prove the effectiveness of the proposed IPS.

This paper addresses system-level design of time- interleaved analog-to-digital converters (TI-ADCs) for ultra-wide band communications. Design space exploration of a TI successive approximation architecture is performed via Monte Carlo simulations, by exploiting behavioral models built bottom-up after characterizing the main ADC blocks in a 90-nm 1-V CMOS technology. Different speed/resolution scenarios are efficiently investigated and the impact of parallelism on system performance, yield and power consumption is assessed starting from the early design phases, finally enabling the selection of two candidate implementations (a 6-bit 4.6- mW and a 7-bit 8.1-mW ADC targeting 1 GS/s) that effectively trade accuracy for energy efficiency and area.

This paper presents a network emulator for rapid prototyping of SpaceWire Intellectual Property cores. SpaceWire is a fault-tolerant high-throughput standard widely used in space and avionic applications. Thanks to its inherent properties, SpaceWire can be effectively adopted for addressing dependability and bandwidth requirements of forthcoming active safety automotive applications. The proposed platform considers both anti-fuse and SRAM FPGA devices. A four-layer software stack ensures full control of prototype features, batch testing and ease of use.

This work presents a low-complexity physical link micro architecture for a mesochronous on-chip communication insensitive to clock skew. This new link architecture, called LIME, integrates a low-latency flow control scheme; this feature may ease the set up of reliable Network-on-Chip infrastructures. The proposed architecture also supports virtual channels that are multiplexed on a single physical link. LIME can be integrated in a conventional digital design flow since it is implemented by means of standard cells only.

Clock distribution is an important issue when designing multi processor systems-on-chip on deep sub-micron technology nodes and non-synchronous approaches are becoming popular in this field. This work presents a low-complexity link microarchitecture for mesochronous on-chip communication that enables skew constraint looseness in the clock tree synthesis, frequency speed-up, power consumption reduction and faster back-end turnarounds. With respect to the state of the art, the proposed link architecture stands for its low power and low complexity overheads; moreover it can be easily integrated in a conventional digital design flow since it is implemented by means of standard cells only. Results are presented referring to the link integrated within a multi processor tiled architecture based on a network-on-chip communication backbone on a CMOS 65 nm technology.

The amount of electronic systems introduced in vehicles is continuously increasing: X-by-wire, complex electronic control systems and above all future applications such as automotive vision and safety warnings require in-car reliable communication backbones with the capability to handle large amount of data at high speeds. To cope with this issue and driven by the experience of aerospace systems, the SpaceWire standard, recently proposed by the European space agency (ESA), can be introduced in the automotive field. The SpaceWire is a serial data link standard which provides safety and redundancy and guarantees to handle data-rates up to hundreds of Mbps. This paper presents the design of configurable SpaceWire router and interface hardware macrocells, the first in state of the art compliant with the newest standard extensions, Protocol Identification (PID) and remote memory access protocol (RMAP). The macrocells have been integrated and tested on antifuse technology in the framework of an ESA project. The achieved performances of a router with 8 links, 130 Mbps data-rate, 1.5 W power cost, meet the requirements of future automotive electronic systems. The proposed networking solution simplifies the connectivity, reducing also the relevant volume and mass budgets, provides network safety and redundancy and guarantees to handle very high bandwidth data flows not covered by current standards as CAN or FlexRay

This paper presents an environment for the automatic generation of FFT/IFFT cores. The cores are derived from a pipelined cascade architecture template supporting run-time programmable length, transform type selection and three different machine arithmetics (fixed-point, block floating-point and convergent block floating-point). The tool profiles arithmetics and generate the macrocell with the minimum operands bit-width (hence minimum circuit complexity) within the numerical accuracy budget given by the target application. Four case studies illustrate the use of the environment in multi-band OFDM communication systems (WLAN, xDSL, DVB-T/H and UWB). Implementation results of the generated macrocells are evaluated on a 65 nm CMOS standard cells library. When compared with other tools for automatic FFT core generation, the proposed environment produces macrocells with lower circuit complexity (gate count, RAM/ROM bits) while keeping the same system level performance (throughput, transform size and numerical accuracy).

This paper presents a design methodology suitable for the cost-effective and real-time implementation of nonlinear image processing algorithms. Starting from high-level functional descriptions the proposed optimization flow simplifies the designer's duty to achieve a low complexity and low power realization in CMOS technology (FPGA and/or ASIC) with low accuracy loss for the implemented algorithm. As an application case study the paper describes the design of a system, based on a Retinex-like algorithm, to improve the visual quality of images acquired in bad lighting conditions.