Digital logic, fault, and error simulation of large VLSI circuits is one of the most compute-intensive tasks in digital systems analysis. This paper describes a massively parallel special purpose array processor, or hardware accelerator, for digital logic, fault, and error simulation. Hardware simulation is a viable approach for simulation of large systems, since simulation time increases rapidly as a function of the size and complexity of the systems to be simulated. In order to reduce the cost and to achieve high performance, a massively parallel array processor and new algorithms have been introduced. By executing an efficient and direct model of the design on the PE array, the architecture can provide high performance, similar to prototyping. Simulation results show that the hardware accelerator is orders of magnitude faster than software simulation.>

Basic data of the nature presented here on fault and design error simulation processes have not been previously reported. Experiments are performed on c-sim, a gate level concurrent simulator developed at the University of Texas at Austin. Three types of statistics are considered: event based statistics, gate evaluation statistics and memory requirements. These statistics are important for design verification researchers and engineers for numerous reasons. For example, they help simulator developers tune up or optimize their concurrent simulators. They also fulfill the increasing need for experimental data concerning design error simulation. Most importantly, these statistics provide guidance to hardware accelerator designers in evaluating and comparing various design options.

The simulation automation system (SAS) was developed to provide an efficient simulation environment, by automating the entire simulation process. This system can be classified, by its salient unique features, into: automatic model generator (AMG), automatic simulator developer (ASD), and design error simulation and test system (DEST). The system can automatically generate multivalued simulation models and automatically develop various simulators, using domain specific automatic programming techniques. The automatic model generation feature can be used when a new model library is built or when an existing library is upgraded. The automatic simulator development feature allows a user who may not be knowledgeable about simulators, to easily develop unique simulators, which can be used for special purposes or special designs. SAS can also verify designs using the Design Error Simulation and Test System. It provides a confidence measure of the verification, as well as simulation results. When users are not satisfied with the confidence level achieved after simulation, they can automatically generate additional simulation patterns for design errors in order to achieve a higher confidence level. Using this approach, design verification time and cost can be considerably reduced, and an actual measure of verification is provided. Consequently, the design cycle can be considerably reduced. This is especially significant for large, complex systems.>

When using simulation for design verification, only a subset of possible simulation patterns is used, since exhaustive simulation is usually not practical. When this subset is used, the designer wants to know how efficiently the design has been verified. The authors provide a measure of simulation pattern effectiveness, based on the concepts of design error modeling. This measure gives insight into the actual level of design validation that has been achieved. These concepts provide a basis for discussing a design validation metric.>

There are many activities included under the category of design automation for integrated circuits. Some of these activities include packaging, placement, routing, interactive graphics, device data bases, and digital simulation; for the purpose of logic verification, timing analysis, and diagnostic test verification. One might also include high-level simulation, such as register transfer simulation, for the purpose of initial logic verification. This paper will be oriented towards modeling and implementation questions which arise when one is attempting to implement an extremely accurate digital simulator for the purposes of logic and design verification and fault simulation. Simulators for these purposes are now extremely important and occupy a major role in any design automation system. These systems are also very expensive and therefore the incorrect answers to a variety of questions which arise during the process of developing such simulators can be disastrous. This paper shall attempt to acquaint the reader with questions that have arisen over the years in terms of developing these simulators and what some of the possible answers are, and their respective tradeoffs. Although the successes, and, equally the failures, of many people have contributed to the present state of the art of digital simulators, one particular simulator, the one the authors are most intimately involved with, will be used as a source of detailed examples demonstrating many of the questions to be discussed.

Diagnosable computer systems are designed to detect and isolate the faults that occur during system operation. A number of techniques are available to the system designer of diagnosable systems. This paper examines a number of these techniques and derives a set of design guidelines incorporating them.