Abraham Sanders, Tomek Strzalkowski, Mei Si, Albert Chang, Deepanshu Dey, Jonas Braasch, Dakuo Wang. Proceedings of the 2022 Conference of the North American Chapter of the Association for Computational Linguistics: Human Language Technologies. 2022.

Based on novel architecture, the 801 minicomputer project has developed a low-level storage manager that can significantly simplify storage programming in subsystems and applications. The storage manager embodies three ideas: (1) large virtual storage , to contain all temporary data and permanent files for the active programs; (2) the innovation of database storage , which has implicit properties of access serializability and atomic update, similar to those of database transaction systems; and (3) access to all storage, including files, by the usual operations and types of a high-level programming language . The IBM RT PC implements the hardware architecture necessary for these storage facilities in its storage controller (MMU). The storage manager and language elements required, as well as subsystems and applications that use them, have been implemented and studied in a prototype operating system called CPR, that runs on the RT PC. Low cost and good performance are achieved in both hardware and software. The design is intended to be extensible across a wide performance/cost spectrum.

The IBM RT PC implements the necessary features of 801 storage architecture. The upper 4 bits of a 32-bit short address select one of 16 segment registers. A 12-bit segment id from the register replaces the 4 bits to form a 40-bit long virtual address. This creates a single large space of 4096 256M-byte segments. Only the supervisor may load segment registers and may therefore control access to and sharing of segments. A long virtual address is translated to real by an inverted page table, in which each entry contains the virtual page address currently allocated to a real page. Hardware searches the table using chained hashing. If a given virtual address is found in a table entry, the index of that entry is the desired real page address. Table size is related only to real storage size rather than to virtual size as with conventional segment and page tables. The inverted page table includes a transaction locking mechanism. Each entry contains bits to represent read and write locks, for 128-byte lines within the page, granted to the transaction id also in the entry. Lock fault interrupt occurs when storage access by the current transaction (id in a register) is not permitted by locks and id in a table entry. Page protection bits may instead be used when transaction locking is not required.