Enhanced Vehicle-to-Everything (V2X) services require ultra-low latency and robust reliability in end-to-end (E2E) data delivery from producers (e.g., vehicles and roadside units) to consumers (e.g., in-car V2X service applications). One of the candidate data delivery architectures that can meet the stringent requirements is restricting the data delivery path within the network edge by letting an edge server relay data between sources and destinations in its coverage. To that end, edge servers need to equip two important functionalities: 1) a reliable and lightweight data transport protocol to collect data from numerous data sources, and 2) an efficient data streaming platform that delivers collected data to consumers with high throughput and low latency. In this work, we design and implement Kafka- Thor, a Kafka-based high-performance data streaming platform, specifically designed for edge servers to collect and deliver timecritical data for enhanced V2X services. The platform reduces E2E data delivery latency by optimizing the data delivery architecture in Kafka using two novel technologies, the singlepoller, multi-worker (SPMW) architecture and service-specific dynamic batching (SS-batching). Experimental results show that Kafka-Thor significantly improves latency and reliability in E2E data delivery, making enhanced V2X services feasible.

An in-vehicle infotainment (IVI) system is connected to heterogeneous networks such as Controller Area Network bus, Bluetooth, Wi-Fi, cellular, and other vehicle-to-everything communications. An IVI system has control of a connected vehicle and deals with privacy-sensitive information like current geolocation and destination, phonebook, SMS, and driver's voice. Several offensive studies have been conducted on IVI systems of commercialized vehicles to show the feasibility of car hacking. However, to date, there has been no comprehensive analysis of the impact and implications of IVI system exploitations. To understand security and privacy concerns, we provide our experience hosting an IVI system hacking competition, Cyber Security Challenge 2021 (CSC2021). We use a feature-flavored infotainment operating system, Automotive Grade Linux (AGL). The participants gathered and submitted 33 reproducible and verified proofs-of-concept exploit codes targeting 11 components of the AGL-based IVI testbed. The participants exploited four vulnerabilities to steal various data, manipulate the IVI system, and cause a denial of service. The data leakage includes privacy, personally identifiable information, and cabin voice. The participants proved lateral movement to electronic control units and smartphones. We conclude with lessons learned with three mitigation strategies to enhance the security of the IVI system.

Solid State Drives (SSDs) are quickly replacing HDDs not only in laptops but also in servers. Since SSD uses semiconductor, i.e., NAND flash memory, as its storage medium, it locates itself between memory and storage: it is faster but more expensive than HDD, and slower but cheaper than DRAM. Meanwhile, big data processing systems require both faster storage and larger memory. While lots of works have been conducted on evaluating the performance enhancement in big data processing systems by replacing HDD with SSD, the effect of SSD as a simple memory extension, i.e., Swap device, has not been studied, sufficiently. In this paper, we investigate the feasibility of using SSD as a swap device for big data processing systems through extensive experiments. Experimental results show that 1) incredibly large amount of IO's are issued to swap device when the physical memory cannot accommodate all data for processing, 2) SSD processes IO's to a swap device significantly faster than HDD, 3) using SSD as a storage device is a far better choice than using it as a swap device, and 4) enterprise SSD is not cost effective when it is used as a swap device.

Multiprocessor embedded software presents major challenges including the increased complexity and stringent performance requirements raised by parallel processing capability. Although component-based approaches can greatly alleviate the complexity problem, traditional approaches do not provide adequate support for performance requirements on multiprocessors. In this paper, we extend component-based approaches for performance-aware design and analysis of multiprocessor embedded software. The proposed approach begins with a component model that is able to capture concurrent and performance-critical behavior based on UML activity diagrams. It then identifies and exploits potential sources of concurrency within components to produce a multithreaded software design targeted at multiprocessors. We also provide a schedulability analysis that can be used for validating multithreaded software design from a temporal perspective.

In this paper, we present a model-driven approach to RTOS-based embedded software development and an automated tool that can produce RTOS-specific code. Our contributions are two fold. First, we defined generic RTOS APIs (application programming interfaces) that can capture most of typical RTOS services but are not bound to any specific RTOS. The generic RTOS APIs can be used as a means for describing application's RTOS-related behavior at an early design stage. We then developed an automated transformation tool that can generate functional code by transforming generic RTOS APIs into RTOS-specific APIs. Our tool, called TransPI, is able to produce 'C' code aimed at POSIX-compliant RTOSs, and is also configurable to target other RTOSs that do not conform to the POSIX standard

This paper formulates a problem of embedded real-time system re-engineering and presents a systematic solution. Embedded real-time system re-engineering is defined as an understanding and alteration of a legacy system to guarantee newly imposed performance requirements. The performance requirements may include a real-time throughput and an input-to-output latency. The proposed approach is based on bottleneck analysis and nonlinear optimization. The inputs to the approach include a system design specified with a process network accompanied by task graphs and task schedules, and a new real-time throughput requirement specified as a system's period constraint. The output is a set of scaling factors that represent the ratios of performance upgrades for processing elements. The solution approach works in two steps. First, it identifies bottleneck processes by estimating process latencies and by analyzing resource sharing among processes. It then derives a set of linear constraints from the new throughput requirement for bottleneck processes. Second, it formulates an integer nonlinear optimization problem and solves it for scaling factors with an objective of minimizing the hardware upgrade cost. Resultant scaling factors are used for cost-effective upgrades of processing elements. To efficiently find feasible solutions, we propose the k-level diagonal search algorithm which runs in a polynomial time with respect to the number of processing elements. Simulation results also confirm this assertion.

Discretely synchronized, distributed real-time systems may suffer from a time discontinuity problem in that local clocks observe the disappearance or reappearance of time intervals. This problem occurs since traditional discrete clock synchronization algorithms adjust local clocks instantaneously. Such time discontinuities may lead to runtime faults due to the loss or gain of critical time points such as task release times and deadlines. In this paper, we propose a dynamic constraint transformation technique we call a constraint transformation for equi-continuity (CTEC) to correctly enforce timing requirements in a distributed real-time system possessing periodically synchronized distributed local clocks. While continuous clock synchronization is generally suggested to avoid the time discontinuity problem, it incurs too much runtime overhead to be implemented in software. The proposed CTEC technique can solve the time discontinuity problem without modifying discrete clock synchronization algorithms. The CTEC, working as an added component of discrete clock synchronization, moves timing constraints out of discontinuous time intervals. In doing so, it makes use of a mapping derived from continuous clock synchronization in order to exploit its continuity property. We formally prove the correctness of CTEC by showing that the CTEC with discrete clock synchronization generates the same task schedule as continuous clock synchronization. In order to show the effectiveness of CTEC, we have implemented it on a distributed platform based on the CAN bus and performed extensive experiments. The experimental results indicate that time discontinuities present a consistency problem to real-world systems. They also show that CTEC is an effective solution to the problem while incurring little run-tine overhead.

We describe our experiments on a real-time system design, focusing on design alternatives such as scheduling jitter, sensor-to-output latency, intertask communication schemes and the system utilization. The prime objective of these experiments was to evaluate a real-time design produced using the period calibration method (Gerber et al., 1995) and thus identify the limitations of the method. We chose a computerized numerical control (CNC) machine as our target real-time system and built a realistic controller and a plant simulator. Our results were extracted from a controlled series of more than a hundred test controllers obtained by varying four test variables. This study unveils many interesting facts: average sensor-to-output latency is one of the most dominating factors in determining control quality; the effect of scheduling jitter appears only when the average sensor-to-output latency is sufficiently small; and loop processing periods are another dominating factor of performance. Based on these results, we propose a new communication scheme and a new objective function for the period calibration method.