A challenging and interesting issue for the solution of large electromagnetic problems is the efficient, sufficiently accurate modeling of the broadband skin-effect loss for conducting planes and 3-D shapes. The inclusion of such models in an electromagnetic (EM) solver can be very costly in compute time and memory requirements. These issues are particularly important for the class of signal, power, and noise integrity (NI) problems. In this paper, we concentrate on partial element equivalent circuit (PEEC)-type methods which are suitable for the solution of this class of problems. Progress has been made recently in the design of skin-effect models. The difficult issues are broadband frequency-domain or time-domain problems. These models are considered in this paper. We present several solution methods, and we compare results obtained with these approaches.

The partial element equivalent circuit (PEEC) approach has been used in different forms for the computation of equivalent circuit elements for quasi-static and full-wave electromagnetic models. In this paper, we focus on the topic of large scale inductance computations. For many problems as part of PEEC modeling, partial inductances need to be computed to model interactions between a large numbers of objects. These computations can be very time and memory consuming. To date, several techniques have been devised to reduce the memory and time required to compute the partial inductance entities, as well as the time required to use them in a circuit analysis compute step. Some of the existing methods use hierarchical compression while some others are based on issues like properties of the inverse of the partial inductance matrix. However, because of inherent limitations, most of these methods are less suitable for PEEC applications. In this paper, we present an approach which is based on the compression of the partial inductance matrix utilizing the QR decomposition of the far coefficients submatrices. The QR-decomposed form is represented as a compressed SPICE-compatible circuit. This yields an efficient and mathematically consistent approach for reducing the storage and time requirements

A key use of the partial element equivalent circuit (PEEC) method is the solution of combined electromagnetic and circuit problems as they occur in many situations such as today's integrated circuit (VLSI) systems and as components in mobile devices. The method, which has been applied to a multitude of electrical interconnect and package problems, is very flexible since it is easy to add new features to the approach. However, faster solutions are of interest since the problems to be solved are continuously increasing size. A class of fast methods is evolving based on the faster evaluation of the matrix elements and the use of iterative or other matrix solvers of the resultant system for the frequency domain. Fast circuit matrix solvers are easier to obtain in the time domain than the frequency domain since the delay or retardation can be utilized to sparsify the circuit matrix. In this paper, we concentrate on techniques for the fast evaluation of the PEEC circuit element for both the frequency and time domain where possible since both are important for the solution of specific problems.

This paper gives an overview of the BlueGene/L Supercomputer. This is a jointly funded research partnership between IBM and the Lawrence Livermore National Laboratory as part of the United States Department of Energy ASCI Advanced Architecture Research Program. Application performance and scaling studies have recently been initiated with partners at a number of academic and government institutions,including the San Diego Supercomputer Center and the California Institute of Technology. This massively parallel system of 65,536 nodes is based on a new architecture that exploits system-on-a-chip technology to deliver target peak processing power of 360 teraFLOPS (trillion floating-point operations per second). The machine is scheduled to be operational in the 2004-2005 time frame, at price/performance and power consumption/performance targets unobtainable with conventional architectures.

High frequency on-chip interconnect examples are accurately analyzed using full-wave PEEC (Partial Element Equivalent Circuit) analysis. All wire currents and voltages (or delays) are visualized using 3D animations to aid intuitive understanding of new, high frequency interconnect effects.

The rapid growth of the electrical modeling and analysis of the interconnect structure, both at the electronic chip and package level, can be attributed to the increasing importance of the electromagnetic properties of the interconnect circuit on the overall electrical performance of state-of-the-art very large scale integration (VLSI) systems. With switching speeds well below 1 ns in today's gigahertz processors, and VLSI circuit complexity exceeding the 100 million transistors per chip mark, power and signal distribution is characterized by multigigahertz bandwidth pulses propagating through a tightly coupled three-dimensional wiring structure that exhibits resonant behavior at the upper part of the spectrum. Consequently, in addition to the inductive and capacitive coupling, present between adjacent wires across the entire frequency bandwidth, distributed electromagnetic effects, manifested as interconnect-induced delay, reflection, radiation, and long-range nonlocal coupling, become prominent at high frequencies, with a decisive impact of overall system performance. The electromagnetic nature of such high-frequency effects, combined with the geometric complexity of the interconnect structure, make the electrical design of today's performance-driven systems extremely challenging. Its success is heavily dependent on the availability of sophisticated electromagnetic modeling methodologies and computer-aided design tools. This paper presents an overview of the different approaches employed today for the development of an electromagnetic modeling and simulation framework that can effectively tackle the complexity of the interconnect circuit and facilitate its design. In addition to identifying the current state of the art, an assessment is given of the challenges that lie ahead in the signal integrity-driven electrical design of tomorrow's performance- and/or portability-driven, multifunctional ULSI systems.

With the advances in the speed of high-performance chips, inductance effects in some on-chip interconnects have become significant. Specific networks such as clock distributions and other highly optimized circuits are especially impacted by inductance. Several difficult aspects have to be overcome to obtain valid waveforms for problems where inductances contribute significantly. Mainly, the geometries are very complex and the interactions between the capacitive and inductive currents have to be taken into account simultaneously. In this paper, we show that a full-wave partial element equivalent circuit method, which includes the delays among the partial elements, leads to an efficient solver enabling the analysis of large meaningful problems. Applying this method to several examples leads to helpful insights for realistic very large scale integration wiring problems. It is shown in this paper that the impact overshoot, reflections, and inductive coupling are critical for the design of critical on-chip interconnects.

Article Free Access Share on Dealing with inductance in high-speed chip design Authors: Phillip Restle IBM T.J. Watson Research Center, Yorktown Heights, NY IBM T.J. Watson Research Center, Yorktown Heights, NYView Profile , Albert Ruehli IBM T.J. Watson Research Center, Yorktown Heights, NY IBM T.J. Watson Research Center, Yorktown Heights, NYView Profile , Steven G. Walker IBM T.J. Watson Research Center, Yorktown Heights, NY IBM T.J. Watson Research Center, Yorktown Heights, NYView Profile Authors Info & Claims DAC '99: Proceedings of the 36th annual ACM/IEEE Design Automation ConferenceJune 1999 Pages 904–909https://doi.org/10.1145/309847.310096Published:01 June 1999Publication History 23citation453DownloadsMetricsTotal Citations23Total Downloads453Last 12 Months58Last 6 weeks7 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF

A methodology is presented for the simulation of electromagnetic noise interactions in packaged low-power electronics using circuit-based models. The availability of such a methodology provides for a unified approach to the modeling of crosstalk, simultaneous switching noise, as well as all other types of noise interactions that impact signal integrity and component/system internal and external electromagnetic compatibility, using a simulation environment that is very compatible with existing circuit simulators such as SPICE. Illustrative examples from noise interactions in mixed-signal analog/digital circuits are used to demonstrate the unique capabilities of the proposed electromagnetic modeling methodology.

Article Frequency domain microwave modeling using retarded partial element equivalent circuits Share on Authors: Hansruedi Heeb View Profile , Saila Ponnapalli View Profile , Albert E. Ruehli View Profile Authors Info & Claims DAC '93: Proceedings of the 30th international Design Automation ConferenceJuly 1993 Pages 702–706https://doi.org/10.1145/157485.165097Published:01 July 1993 3citation234DownloadsMetricsTotal Citations3Total Downloads234Last 12 Months0Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access

With ever increasing clock frequencies, accurate 3-D interconnect analysis in chips and packages is becoming a necessity. The retarded partial element equivalent circuit (rPEEC) method has been successfully applied to 3-D analysis but for large problems it becomes expensive in CPU and memory usage, and in time domain it sometimes has numerical problems. Complex frequency hopping (CFH), a new multi-point moment-matching technique, is expanded to handle retarded networks. CFH speeds up rPEEC frequency domain analysis of large frequency bands significantly. It also allows the efficient calculation of resonances and - most importantly - enables time domain modeling of rPEEC networks that have so far resisted analysis by any other method.

A general approach for modeling 3-D layout geometries is presented. In particular, the partial-element equivalent circuit (PEEC) technique has been used successfully to model interconnect structures for chips and packages. The technique, which is circuit based, permits the electrical modeling of arbitrary 3-D geometries and allows 3-D transmission line properties to be analyzed. Recently, the technique has been extended to include retardation and dielectric layers. The authors have experimented with the use of the asymptotic waveform evaluation (AWE) approach to speed up the solution of the resulting circuit equations.>

It is shown that retardation effects, due to the finite speed of electromagnetic interactions, play a significant role for PC-board interconnects. It is demonstrated that in some cases errors of more than an order of magnitude result in some frequency components when retardation is neglected. Extensions to a circuit simulator are introduced that make it possible to do retarded circuit simulation. Specifically, an algorithm to extend SPICE-level simulators to include retardation is presented. Comparisons with analytical equations, the method of moments, and with measurements show good agreement.>

A realistic approach is introduced for the computation of the electromagnetic radiation interference (EMI) from printed circuit boards. The approach is suitable for large problems and real circuit boards can be investigated. Each trace and its source and loads are represented as electrical circuits and a conventional time-domain circuit simulation is used to find the currents. The field is then calculated by applying the free-space Green's function to all currents including the polarization currents. This is, to the authors' knowledge, the first CAD tool which can predict EMI from basic principles.>

An analysis tool is introduced that measures subcircuit coupling and error attenuation in waveform relaxation (WR) circuit simulation algorithms with full dimensionality. Unlike current methods that use heuristics to calculate scalar gains, this method capture all the effects of error attenuation over time and space. An example is provided of how this technique can be used to study the performance of various partitions, schedules, and WR algorithms on a wide range of technologies, including BiCMOS.>

The time-domain modeling of the connections in a high-speed computer is such of a complexity that practical problems can only be solved using suitable approximations. Presented are the results of a time-domain modeling work where a novel and faster representation of the capacitances has been developed. Instead of a circuit with O(n/sup 2/) capacitances (where n is the number of conductors), an equivalent circuit of n pseudo-capacitances and n dependent voltage sources is used. Due to the increased sparsity of the simulation matrix, the method considerably speeds up the SPICE or ASTAP compute time. In addition, pseudo-capacitances and voltage sources can be calculated from the coefficient of potential matrix, thus making the calculation of the capacitance matrix unnecessary. This reduces the computational complexity of the capacitance extraction O(n/sup 3/) to O(n/sup 2/) resulting in another major speed-up.>

The Waveform Relaxation (WR) method is an iterative method for analyzing nonlinear dynamical systems in the time domain. The method, at each iteration, decomposes the system into several dynamical subsystems each of which is analyzed for the entire given time interval. Sufficient conditions for convergence of the WR method are proposed and examples in MOS digital integrated circuits are given to show that these conditions are very mild in practice. Theoretical and computational studies show the method to be efficient and reliable.