Implantable wireless neural recording from a large ensemble of simultaneously acting neurons is a critical component to thoroughly investigate neural interactions and brain dynamics from freely moving animals. Recent researches have shown the feasibility of simultaneously recording from hundreds of neurons and suggested that the ability of recording a larger number of neurons results in better signal quality. This massive recording inevitably demands a large amount of data transfer. For example, recording 2000 neurons while keeping the signal fidelity ( > 12 bit, > 40 KS/s per neuron) needs approximately a 1-Gb/s data link. Designing a wireless data telemetry system to support such (or higher) data rate while aiming to lower the power consumption of an implantable device imposes a grand challenge on neuroscience community. In this paper, we present a wireless gigabit data telemetry for future large-scale neural recording interface. This telemetry comprises of a pair of low-power gigabit transmitter and receiver operating at 60 GHz, and establishes a short-distance wireless link to transfer the massive amount of neural signals outward from the implanted device. The transmission distance of the received neural signal can be further extended by an externally rendezvous wireless transceiver, which is less power/heat-constraint since it is not at the immediate proximity of the cortex and its radiated signal is not seriously attenuated by the lossy tissue. The gigabit data link has been demonstrated to achieve a high data rate of 6 Gb/s with a bit-error-rate of 10(-12) at a transmission distance of 6 mm, an applicable separation between transmitter and receiver. This high data rate is able to support thousands of recording channels while ensuring a low energy cost per bit of 2.08 pJ/b.

Electrical stimulation in eyelid reanimation has been verified in previous studies as a potential treatment for facial nerve paralysis. Design challenges, including physical pain during stimulation, reducing the latency between the natural blink and the artificial blink, and patient-to-patient differences, make it difficult to build this system. In this paper, the design challenges are analyzed in detail, based on which a closed-loop electrochemical stimulation system is proposed. Using our system, real-time blink detection and electrical stimulation have been verified with FPGA and ASICs. Area of the proposed fully integrated chip, including electromyography (EMG) amplifier, blink detection processor, reduced instruction set computer (RISC), and current stimulator, is estimated to be 11.46mm2in 0.35um CMOS process.

Principal component analysis (PCA) spike sorting hardware in an integrated neural recording system is highly desired for wireless neuroprosthetic devices. However, a large memory is required to store thousands of spike events during the PCA training procedure, which impedes the on-chip implementation for the PCA training engine. In this paper, a mean pre-estimation method is proposed to save 99.01% memory requirement by breaking the algorithm dependency. According to the simulation result, 100 dB signal-to-error power ratio can be preserved for the resulting principal components. According to the implementation result, 6.07 mm2silicon area is required after a 283.16 mm2area saving for the proposed PCA training hardware.

An emerging class of neural prostheses aims to provide more aggressive performance by realizing advanced realtime signal processing algorithms in particular the spike sorting on chips. To support realtime spike sorting for 128 channels, the traditional fully parallel approach duplicating 128 processing units results in a large burden on chip area. The fully folding approach sharing one processor over 128 channels consumes large dynamic power in data caching. We propose to use the parallel-folding structure to optimally tradeoff the area and power. Our 128-channel spike sorting processor consumes 1.36 mm2area and 1.87 mW power in 90 nm process. 91.1% and 63.4% of the hardware resources (area×power) are reduced compared to the fully parallel and the fully folding approaches respectively.

This paper presents a low-power neural amplifier for multi-channel neural recording systems. To achieve low power consumption and small die area, the single-branch amplifier, based on CMOS inverter, is employed along with a capacitive feedback loop. This amplifier has a gain of 28.9 dB and operates from plusmn0.9 V. The low-frequency cutoff is able to be varied from less than 100 Hz by adjusting the tuning voltage and the high-frequency cutoff is fixed at 11.2 KHz. The input-referred noise of this amplifier is 14.5 muVrmsand it consumes a power of 220 nW. This low-power neural amplifier is fabricated in 0.35 mum CMOS process with active die areas of 200 mu times100 mum.

Studying signal and noise properties of recorded neural data is critical in developing more efficient algorithms to recover the encoded information. Important issues exist in this research including the variant spectrum spans of neural spikes that make it difficult to choose a global optimal bandpass filter. Also, multiple sources produce aggregated noise that deviates from the conventional white Gaussian noise. In this work, the spectrum variability of spikes is addressed, based on which the concept of adaptive bandpass filter that fits the spectrum of individual spikes is proposed. Multiple noise sources have been studied through analytical models as well as empirical measurements. The dominant noise source is identified as neuron noise followed by interface noise of the electrode. This suggests that major efforts to reduce noise from electronics are not well spent. The measured noise from in vivo experiments shows a family of 1/f^{x} (x=1.5\pm 0.5) spectrum that can be reduced using noise shaping techniques. In summary, the methods of adaptive bandpass filtering and noise shaping together result in several dB signal-to-noise ratio (SNR) enhancement.

This paper presents a 4-channel wearable wireless neural recording system that consists of wireless head stage, receiver board, and user interface software. The wireless head stage is implemented using a custom designed font-end IC for bio potential amplification, filtering, and channel selection and a commercial analog FM transmitter chip. Adjustable gain and bandwidth of the channel allows the system to be used in recording various neural signals. The size of the head stage is 1.55" times 1.725" times 0.5" and the weight is 20 g. The power consumption of the head stage is 28 mW from two 1.55 V button cell batteries that allows continuous operation of at least 15 hours. The system was tested for ex-vivo and in-vivo extracellular recordings from a dissected snail brain and a live rat respectively.

This paper presents a spike feature extraction algorithm that targets real-time spike sorting and facilitates miniaturized microchip implementation. The proposed algorithm has been evaluated on synthesized waveforms and experimentally recorded sequences. When compared with many spike sorting approaches our algorithm demonstrates improved speed, accuracy and allows unsupervised execution. A preliminary hardware implementation has been realized using an integrated microchip interfaced with a personal computer.

This paper presents a MICS (medical implant communication service) based body sensor network design and implementation for patient physiological data collection for health monitoring purposes. The MICS band offers the advantage of miniaturized electronic devices that can either be used as an implanted node or as an external node. In this work, a prototype sensor network is implemented by incorporating temperature and pulse rate sensors on nodes. Each developed sensor node has the capability of physiological data acquisition and local processing. The sensor node can also transmit data over the air to a remote central control unit (CCU) for further processing and storage. The developed system offers medical staff to obtain patient's physiological data on demand basis via the Internet. Moreover, the system has been optimized for power consumption by using a polling architecture. Some preliminary performance data is presented in the paper.

An all-digital symbol timing recovery technique that uses a 1-bit ADC, delay-XOR unit and a digital prefilter before the all-digital loop is analyzed. This approach provides a low-power, all-digital implementation in CMOS integrated circuit and exhibits very low jitter. The prefilter is arranged to eliminate frequency offsets on the input signal. The system is robust against fast and large Doppler shift and is therefore well suited for receivers in satellite applications. A symbol timing circuit based on this technique has been implemented for a wide range of bit rates (0.1-100 Kbps). It is synchronized within 3 or 4 bits in the presence of high carrier frequency offsets. A detailed performance study is carried out by both analytical simulation and hardware implementation to provide guidelines when the proposed scheme is applied to other transmission systems.

A neural recording system for monitoring the behavior of sharks is presented. The system consists of an electrode array made of silicon neuroprobes that interface with a flexible parylene cable that connects the electrode array to the electronics to process the neural signals, and a wireless transmission system that transmit the processed signals to the external world. The electronics include amplifiers, multiplexers, analog-to-digital converters, a FPGA, a telemetry chip. The results of the chip designs of amplifier are reported. The challenges in realizing a miniaturized, low power and high density (more than 100 recording sites) recording system are outlined. The choice of architecture and the tradeoffs involved are described

Based on the effective attenuation constant approximation of distributed RLC lines, simplified design guidelines are presented dealing with the line characteristics, termination, and delay estimation of on-chip global interconnects. RC delay models are verified to be still accurate for a wide range of parameters conventionally considered inductive. A new closed-form RLC delay formula is developed when RC models are inadequate. The formula works for both voltage and current-mode signaling and exhibits 10% accuracy of SPICE simulation. This work is suitable for global routing topologies and iterative layout optimization.

This brief describes an adaptive bandwidth bus architecture based on hybrid current/voltage mode repeaters for long global RC interconnect static busses that achieves high-data rates while minimizing the static power dissipation associated with current-mode (CM) signaling. An experimental adaptive bandwidth bus test chip fabricated in AMI 1.6-/spl mu/m Bulk CMOS indicates a reduction in power dissipation of approximately 62% over CM sensing and an increase in maximum data rate of 40% over voltage-mode signaling.

This paper describes a low-power design methodology for a bus architecture based on hybrid current/voltage mode signaling for deep sub-micrometer on-chip interconnects that achieves high data transmission rates while minimizing the number of repeaters by nearly 1/3. The technique uses low-impedance current-mode sensing to increase the data throughput and minimizes the static power dissipation inherent to current-mode signaling by adaptively changing the interconnection bandwidth given a change in input signal activity. Since bandwidth is related to power dissipation, the adaptive bus attains energy efficient data transmission by expending minimum power required to support the bus signal activity.The design method is based on statistical analysis of address streams extracted for typical benchmark programs using a microprocessor time-based simulator in combination with circuit-level power analysis. Simulation results indicate improvements in power dissipation of up to 65% and 40% over current and voltage mode signaling schemes, respectively.

This paper addresses propagation delay and power dissipation for current mode signaling in deep submicrometer global interconnects. Based on the effective lumped element resistance and capacitance approximation of distributed RC lines, simple yet accurate closed-form expressions of delay and power dissipation are presented. A new closed-form solution of delay under step input excitation is first developed, exhibiting an accuracy that is within 5% of SPICE simulations for a wide range of parameters. The usefulness of this solution is that resistive load termination for current mode signaling is accurately modeled. This model is then extended to a generalized delay formulation for ramp inputs with arbitrary rise time. Using these expressions, the optimum-line width that minimizes the total delay for current mode circuits is found. Additionally, a new power-dissipation model for current-mode signaling is developed to understand the design tradeoffs between current and voltage sensing. Based on the results and derived formulations, a comparison between voltage and current mode repeater insertion for long global deep submicrometer interconnects is presented.

Clock skew optimization is a timing technique to improve system performance by employing scheduled skews at flip-flops. The integrated framework presented here includes a new linear programming (LP) formulation for the clock skew optimization problem. In this work, we use the concept of a global time frame, instead of a local one, to find a set of optimal skews to minimize system cycle time. The framework provides a firm theoretical foundation for scheduling skews into existing designs. Furthermore, we extend the LP formulation to accommodate retiming in the optimization process. Our framework allows for concurrent timing optimization of a design by retiming the circuit and scheduling clock skews at flip-flops. It is shown that this optimization can be formulated as a mixed-integer linear program and significantly reduce the clock period.

We suggest a new technique to reduce energy consumption in the processor datapath without sacrificing performance by exploiting operand value locality at run time.Data locality is one of the major characteristics of video streams as well as other commonly used applications.We use a cache-like scheme to store a selective history of computation results, and the resultant Te-e-21se leads to power savings. The cache is indexed by the OpeTandS.Based on OUT model, an 8 to 128 entry execution cache TedUCeS power consumption by 20% to 60%.

Many techniques have been proposed to optimize digital system timing. Each technique can be advantageous in particular applications, however they are most often applied individually rather than concurrently. The framework presented here allows for concurrent timing optimization using retiming, intentional clock skew, and wave pipelining for latch-based designed systems with single or multi-phase clocking. This optimization is formulated as a mixed integer linear program. Our integrated framework also includes a new optimization technique called resynchronization which allows for the insertion of latches in the shortest paths and thus avoids race conditions. Our work has been applied to several designs and is able to significantly reduce the clock period.

This paper presents an architecture for generating a high-speed data pattern with precise edge placement (resolution) by using the matched delay technique. The technique involves passing clock and data signals through arrays of matched delay elements in such a way that the data rate and resolution of the generated data stream are controlled by the difference of these matched delays. This difference can be made much smaller than an absolute gate delay. Since the resolution of conventional designs is determined by these absolute delays, the matched delay technique yields a much finer resolution as well as higher speeds than traditional methods. The matched delay technique lends itself to high-precision and high-speed applications such as fast network interfaces or test pattern generators. This paper also describes a matched delay data generator submitted for fabrication in a MOSIS 1.2 /spl mu/m CMOS technology. Simulations indicate that data signals with on-chip bit rates of 833 Mb/s and resolutions of 100 ps can be generated.

A stochastic global optimization approach is presented for transistor sizing in CMOS VLSI cir cuits.This is a direct search strategy for the best design among feasible ones, with the designer determining when the search is stopped.Through examples, we show the power of this technique in quickly obtaining very good designs, for skew minimization problems.

Wave-pipelining is a timing methodology used in digital systems to achieve maximal rate operation. Using this technique, new data are applied to the inputs of a combinational block before the previous outputs are available, thus effectively pipelining the combinational logic and maximizing the utilization of the logic without inserting registers. This paper presents a timing constraint formulation for the correct clocking of wave-pipelined systems. Both single- and multiple-stage systems including feedback are considered. Based on the formulation of this paper, several important new results are presented relating to performance limits of wave-pipelined circuits. These results include the specification of distinct and disjoint regions of valid operation dependent on the clock period, intentional clock skew, and the global clock latency. Also, implications and motivations for the use of accurate delay models and exact timing analysis in the determination of combinational logic delays are given, and an analogous relationship between the multi-stage system and the single-stage system in terms of performance limits is shown. The minimum clock period is obtained by clock skew optimization formulated as a linear program. In addition, important special cases are examined and their relative performance limits are analyzed.>

In computer vision and image processing, the high degree of parallelism and pipelining of algorithms is often obstructed by the raster-scan I/O constraint and the information growing property of multiresolution structures. The approach of formulating algorithms in the pyramid structure as a binary tree structure, and mapping the binary tree structure into a linear pipelined array of 2logN levels for N*N images using a first-in, first-out technique (FIFO) to emulate the tree connections is proposed. It turns out that several geometric feature extraction algorithms such as moment generation can be represented in this scheme so that the inherent information growing of the algorithms enables the exploitation of bit-level concurrency in the architectural design. Consequently, the design of pipelined processor at each level is significantly simplified using bit-serial arithmetic, and this VLSI architecture is capable of generating moments concurrently in real-time.>

The authors present the organization of an interleaved wrap-around memory system for a partitionable parallel/pipeline architecture with P pipes of L processors each. The architecture is designed to efficiently support real-time image processing and computer vision algorithms, especially those requiring global data operations. The interleaved memory system makes the architecture highly scalable in that L and P can be chosen to optimize performance for particular problems and reconfigurable in that, once L and P are fixed, problems of any size can still be mapped onto the architecture. The authors demonstrate techniques and methods for mapping computational structures to the architecture by considering the case of the 1-D butterfly network (1DBN). Since many other computational structures can be mapped to 1DBN, this gives a firm application base for the architecture. The authors also demonstrate methods for scheduling and controlling the memory system.>

A high-performance partitionable parallel/pipeline architecture (P/sup 3/A) that is capable of real-time image processing is discussed. The architecture consists of P disjoint pipes of L processors each, connected together through a novel wraparound memory. Many different problem classes, including shuffle-exchange, butterfly, and tree algorithms, can be easily mapped into P/sup 3/A. The power of the architecture lies in its ability to exploit both the spatial and temporal aspects of concurrency balancing parallelism and pipelining.>

A theoretical study which allows determination of the minimum number of vias for realizable multilayer channel routing under a topological model is presented. The theory is sufficiently general to solve a variety of problems under different technological constraints, e.g. VLSI multilayer switchbox and channel routing, through-hole printed circuit board (PCB) channels, and single-layer routing. Topological routing is concerned with wire intersection but not area, zero-width wires and zero-area vias being assumed. Unconstrained via minimization (UVM) is not constrained to a prerouted topology. This paper presents restrictive cases of UVM, finding most to be NP-hard, but the case resulting from constraints of traditional switchbox or channel routing to be solvable in O(kn/sup 2/), where k is the maximum number of pins of a net layer and n is the number of pins. The minimum number of vias for various switchbox and channel routing benchmarks are reported.>

The usefulness of the shuffle-exchange network in parallel processing applications is well established. The optimal embedding of a shuffle-exchange network of a given size depends on the number of cycles of the shuffle permutation of that size. The cost of one method of adding fault-tolerance through reconfigurability depends upon the number of such cycles, and the manner in which they can be connected to form larger cycles. An exact equation for the number of cycles of a shuffle of size 2/sup W/ is presented. That result is used to demonstrate that it is always possible to form a Hamiltonian cycle on all processors in a shuffle-exchange connected array. From this, it is apparent that there are a large number of ways of sharing spare processors among the members of many cycles. Thus, redundancy can be supplied in any strength, from adding on a spare processor, to adding one for each cycle of the shuffle.>

An efficient mapping from a tree structure into a pipelined array of 2log N states is presented for processing an N*N image. In the proposed mapping structure the identification of the information growing property inherent in feature-extraction algorithms allows bit-level concurrency to be exploited in the architectural design. Accordingly, the design of each staged pipelined processor is simplified.>

Characteristics and constraints of real-time geometric-feature extraction are discussed. Extracting geometric features from a digital image can be characterized as a computation-intensive task in the environment of a real-time automated vision system. Such tasks require algorithms with a high degree of parallelism and pipelining under the raster-scan I/O constraint. Using the divide-and-conquer technique, many feature extractions have been formulated as a pyramid structure and then mapped into a binary tree. An efficient mapping from a tree structure into a pipelined array of 2logN stages is presented for processing an N*N image. In the proposed mapping structure, the identification of the information growing property allows the exploitation of bit-level concurrency in the architecture design. Accordingly, the design of each staged pipelined processor is simplified containing only bit-serial arithmetic. A single VLSI chip that can generate (p+1)(q+1) moments concurrently in real-time applications is described. This chip has a hardware complexity of O(pq(p+q)log/sup 2/N) units, where p, q stand for the orthogonal orders of the moment. This hardware complexity is better than the O(pq(p+q)/sup 2/log/sup 2/N) units required by the other methods. A single VLSI chip to generate ten moments for a (512*512*8)/pixel image in real time is presented.>

Architectures based on the vector-radix 2DFFT algorithm and hence can avoid the matrix transpose problem have been proposed. The unique feature of the proposed architectures is that the data can be driven into the arithmetic processors in a pipeline fashion. This paper presents a propotype chip, which has been designed in 2 μm NMOS technology, for the generalized butterfly unit. The chip is a two-stage pipelined processor. The design experience, timing information, and the chip features including four multipliers, one adder/subtracter and PLA controllers are presented.